A mainboard port needs to:
- select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT'
- implement the Ada package `GMA.Mainboard' with a single function
`ports' that returns a list of ports to be probed for displays.
- set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use
in romstage (and ramstage) for the graphic device.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=libgfxinit compiles in romstage.
libgfxinit successfully executes in romstage and ramstage using
the requested MMIO setting on skolas.
Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:263920313
TEST=Boot to OS on craask eMMC and NVMe SKUs with both unprovisioned
fw_config and fw_config set correctly.
Change-Id: I4167ee4d00b9ae8fe074c6f5e7a2d5a7382bfe6d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:251055188
TEST=Boot to OS on yaviks eMMC and UFS SKUs with both unprovisioned
fw_config and fw_config set correctly.
On UFS SKU with fw_config set, eMMC no longer shows up in lspci.
(On eMMC SKU, UFS and ISH were already disabled by the coreboot PCI scan
so there's no change in behaviour.)
Change-Id: I31402cb49cffefd98b6fed971f249528448b1d0d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
IFDv1 always has 8 regions, while IFDv2 always has 16 regions.
It's platform specific which regions are used or are reserved.
The 'SPI programming guide' as the name says is a guide only,
not a specification what the hardware actually does.
The best to do is not to rely on the guide, but detect how many
regions are present in the IFD and expose them all.
Very early IFDv2 chipsets, sometimes unofficially referred to as
IFDv1.5 platforms, only have 8 regions. To not corrupt the IFD when
operating on an IFDv1.5 detect how much space is actually present
in the IFD.
Fixes IFD corruption on Wellsburg/Lynxpoint when writing a new
flash layout.
Change-Id: I0e3f23ec580b8b8402eb1bf165e3995c8db633f1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
The patch adds Kconfigs to define scaling factor for Efficient and
Performance cores instead of using hard coded values in the soc code.
Also, the patches uses the Kconfigs directly to calculate the core's
nominal performance. So, we don't need to implement soc function
soc_get_scaling_factor() to get the scaling factor data for different
core types. Hence, soc_get_scaling_factor() function is removed.
TEST=Build the code for Gimble and Rex. Also, I have verified that
build system logs error when the Kconfigs are undefined.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the watchdog timer reaches 0, the timer value won't reset to the
default value unless there is an external reset or a kick. It will
result in the watchdog failing to trigger the reset signal.
We kick the watchdog to reset the timer to the default value. Also,
because WDT hardware needs about 94us to synchronize the registers,
add a 100us delay before triggering the reset signal.
BUG=b:264003005, b:264017048
BRANCH=corsola
TEST= Reboot successfully with the following cmd
stop daisydog
sleep 60 > /dev/watchdog&
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com>
Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When AP boots up after Cr50 firmware update and reboot, AP finds
that Cr50 reset is required for Cr50 to pick the new firmware so
it trigger Cr50 reset and power off the system, AP expects system
will power on automatically after Cr50 reset. However this is not
the case for Chromebox, Chromebox EC set AP_IDLE flag when system
is shutting down, when AP_IDLE flag is set in EC, the system stays
at S5/G3 and wait for power button presssend. It cause an issue in
factory that the operator needs to press power button to power on
the DUT after Cr50 firmware update.
This patch sends EC command to direct EC to clear AP_IDLE flag
after AP shutdown so AP can boot up when Cr50 reset.
BUG=b:261119366
BRANCH=firmware-brya-14505.B
TEST=DUT boots up after Cr50 firmware update in factory test flow
Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces a new config named `DEFAULT_ADL_NEM` and
allows respective brya variants with Alder Lake ESx samples to
choose NEM over eNEM as eNEM was fuse disabled till ESx.
TEST=The boot flow related to eNEM and NEM behaviour remains the
same with and without this patch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
In cases where there are limitations on the mainboard it can be
necessary to limit the used SATA speed even though both, the SATA
controller and disk drive support a higher speed rate. The FSP parameter
'SataSpeedLimit' allows to set the speed limit.
This patch provides a chip config so that this FSP parameter can be
set as needed in the devicetree on mainboard level.
Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71229
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
BUG=b:121309055
TEST=build/boot Windows/linux on multiple dedede variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.
Change-Id: I91e03bd1d96a6b2f0c3813665910133db0d6c308
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I212533ffdfb05f841e722c130b52c2976272e670
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
For touchscreens on dedede variants, drive the enable GPIO high
starting in romstage, then disable the reset GPIO in ramstage. This will
allow coreboot to detect the presence of i2c touchscreens during ACPI
SSDT generation (implemented in a subsequent commit).
Since the fast majority of dedede variants have a touchscreen option,
and those that do use the same GPIOs for enable/reset, set the GPIOs for
touchscreen operation in the baseboard and then override for the few (3)
variants that do not have a touchscreen.
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: Ic216827a4b53d1d35913efca63a43d4672791c54
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The dGPU used for some Brya projects requests 33 bits of address
space for one of its BARs via the Resizable BAR mechanism
(requires 6GB).
This Kconfig is currently set at 32 bits for brya, so the allocation currently is capped at 32 bits (4GB). This patch sets the limit to 33
bits for brya boards, which is enough for the GPU.
BUG=b:214443809
TEST=all of the dGPU PCI BARs on agah can be successfully allocated
Change-Id: Ia791be5108fb07a256ae62fc2aee2f057909ef12
Signed-off-by: Tarun Tuli <tarun@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
get_cpu_index() helper function returns cpu's index based on it's APIC
id position from the ascending order list of cpus' APIC IDs.
In order to calculate the cpu's index, the helper function needs to
traverse through each cpu node to find their APIC IDs. So, the function
traverse the CPU node list from the cpu whose APIC ID is 0 assuming it
is the first cpu node in the list. This logic works fine where BSP's
APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as
APIC ID numbering first get assigned for CPU Die Efficient cores, then
Performance cores.
Please refer section# 6.1 of doc#643504 for more details on APIC IDs.
Considering the APIC Id allotment for MTL cores, as existing code
traversing begins from the cpu that has APIC Id#0 which may not be the
first cpu node in the list so index calculation results in wrong value.
The patch addresses above described issue by traversing all the CPU
nodes to calculate the cpu index. Also, prevents inconsistent report
of /sys/devices/system/cpu/cpu*/cpufreq/* and
/sys/devices/system/cpu/cpuXX/acpi_cppc on each reboot.
TEST=Verified that the get_cpu_index helper function returns the correct
index id for a CPU on Rex.
The coreboot log with code instrumentation, before this patch:
[DEBUG] my_apic_id:0x10 cpu_index: 0x6
[DEBUG] my_apic_id:0x11 cpu_index: 0x6
[DEBUG] my_apic_id:0x42 cpu_index: 0x6
[DEBUG] my_apic_id:0x21 cpu_index: 0x6
[DEBUG] my_apic_id:0x40 cpu_index: 0x6
[DEBUG] my_apic_id:0x31 cpu_index: 0x6
[DEBUG] my_apic_id:0x39 cpu_index: 0x6
[DEBUG] my_apic_id:0xa cpu_index: 0x3
[DEBUG] my_apic_id:0x0 cpu_index: 0x0
[DEBUG] my_apic_id:0x8 cpu_index: 0x2
[DEBUG] my_apic_id:0x4 cpu_index: 0x2
[DEBUG] my_apic_id:0x28 cpu_index: 0x6
[DEBUG] my_apic_id:0x2 cpu_index: 0x1
[DEBUG] my_apic_id:0x38 cpu_index: 0x6
[DEBUG] my_apic_id:0x29 cpu_index: 0x6
[DEBUG] my_apic_id:0xe cpu_index: 0x5
[DEBUG] my_apic_id:0x6 cpu_index: 0x2
[DEBUG] my_apic_id:0x20 cpu_index: 0x6
[DEBUG] my_apic_id:0x30 cpu_index: 0x6
[DEBUG] my_apic_id:0x19 cpu_index: 0x6
[DEBUG] my_apic_id:0xc cpu_index: 0x4
[DEBUG] my_apic_id:0x18 cpu_index: 0x6
We can see same cpu_index for multiple cores before fix.
After this patch..
[DEBUG] my_apic_id:0x10 cpu_index: 0x8
[DEBUG] my_apic_id:019 cpu_index: 0xb
[DEBUG] my_apic_id:0x11 cpu_index: 0x9
[DEBUG] my_apic_id:0x18 cpu_index: 0xa
[DEBUG] my_apic_id:0x40 cpu_index: 0x14
[DEBUG] my_apic_id:0x30 cpu_index: 0x10
[DEBUG] my_apic_id:0x42 cpu_index: 0x15
[DEBUG] my_apic_id:0xc cpu_index: 0x6
[DEBUG] my_apic_id:0x2 cpu_index: 0x1
[DEBUG] my_apic_id:0x29 cpu_index: 0xf
[DEBUG] my_apic_id:0xe cpu_index: 0x7
[DEBUG] my_apic_id:0x20 cpu_index: 0xc
[DEBUG] my_apic_id:0x0 cpu_index: 0x0
[DEBUG] my_apic_id:0x31 cpu_index: 0x11
[DEBUG] my_apic_id:0x28 cpu_index: 0xe
[DEBUG] my_apic_id:0x21 cpu_index: 0xd
[DEBUG] my_apic_id:0xa cpu_index: 0x5
[DEBUG] my_apic_id:0x38 cpu_index: 0x12
[DEBUG] my_apic_id:0x8 cpu_index: 0x4
[DEBUG] my_apic_id:0x4 cpu_index: 0x2
[DEBUG] my_apic_id:0x39 cpu_index: 0x13
Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes the call into TXT lib in order to disable the TXT
if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT
would be helpful to access VGA framebuffer prior calling into FSP-M.
TEST=Able to perform disable_txt and unlock memory which helped to
access VGA framebuffer prior calling into FSP-M.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
