Upon bootup the hardware reads at minimum 256 * 16 bytes (4Kb, or 32KB) over
I2C on a system with all DIMM slots populated. If even one of those reads
has a single flipped bit in it (due to EMI, cross coupling with another trace,
or just poor margins on some cheap DIMM) the system will hang and require a
hard reset. In practice I've seen failure rates as high as 1 failed boot in
50 due to this issue, granted with cheap DIMMs, but even so retrying the read
resolves the corruption issue.
I2C is not designed for continuous data transmission with high reliability, and
there is no hardware error checking, therefore a single retry when transferring
this amount of data makes sense.
Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
All boards using this SuperIO have been removed from the tree already.
Change-Id: I3c43a431d92d76b6ed3ec72b203d3e80925cadea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12247
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
NOTE: This commit switches CacheBase in CAR to use the DCACHE_RAM_BASE
Kconfig variable. There should be no functional difference between
the existing code and the new code, however hardware verfication is
encouraged on lesser used architectures such as AMD Geode.
Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11970
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The build was changed to remove usage of microcode .h files when
all of the .h files were converted to binary. This is still
needed for some builds when microcode binaries aren't in the
blobs tree.
Change-Id: Ia323c90efe8aa0b8799fc5cce6197509e466a105
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12333
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This is an update to the script in the blobs repo that converts
individual or multiple files into a microcode binary.
Change-Id: I66fb650bbfa334d1f07e8e3914ef6deb8e72bbb4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12332
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The obsolete and removed getpir utility remarked in its output that the
data is autogenerated. The tool was removed because it wasn't very
reliable, so there's no need to point that anymore.
Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12354
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
'edid->hdmi_monitor_detected' would indicate whether the monitor
interface is HDMI or DVI.
BRANCH=none
BUG=chrome-os-partner:43789
TEST=Previously, my LG monitor couldn't show dev screen. But now I can see
dev screen have been posted normally.
Change-Id: Id71f051b2cd792712e52bee7a763db383c1962a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88101589a22d06f0bc25e0750b2862cf66b55391
Original-Change-Id: I157861d327926b834e1e8606b0b676f413491c70
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309056
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12346
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
HDMI driver need to know whether the monitor is DVI
or HDMI interface, so this commit just introduce a
new number 'hdmi_monitor_detected' to struct edid.
There were four bits to indicate the monitor interfaces,
it's better to take use of that. But those bits only
existed in EDID 1.4 version, but didn't persented in
the previous EDID version, so I decided to detect the
hdmi cea block.
BRANCH=none
BUG=chrome-os-partner:43789
TEST=When mickey connect with HDMI monitor, see 'hdmi_monitor_detected' is 'true'.
When mickey connect with DVI monitor, see 'hdmi_monitor_detected' is 'false'.
Change-Id: I1a4f1410e1cce1474ffae858db161a18578cac3a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 409f041805d9fdff2d49faa1a3a262cf4dc609c2
Original-Change-Id: Ife770898b0f2b4f58b8259711101a0cab4a5e4ac
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309055
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4.
2. DDR4 uses different memory configuration in AGESA.
Pass memory configuration parameters in agesawrapper_amdinitpost.
3. Tested on Rev C and Rev F.
Both of them can boot to Windows 8 and have the correct memory size.
Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11733
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Bettong uses 3 GPIO(5-7) pins to identify board.
The GPIO ports are mapped to MMIO space.
The GPIO value and board version are mapped as follow:
GPIO5 GPIO6 GPIO7 Version
0 0 0 A
0 0 1 B
......
1 1 1 H
Change-Id: I72df28043057d8c4ccc4a2e645011ca5379e9928
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11732
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The RAM voltages can be set per socket, which contains two nodes.
Only reset the allowed voltages per socket before processing a new socket and
not after every node.
Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12297
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The Ultra 40 M2 is a dual Socket F workstation with MCP55/IO55 chipset,
DME1737 superio and onboard Firewire. This board port is for family
0Fh (K8) processors.
Due to existing bugs, having memory on the second node will cause
raminit to fail.
Change-Id: I5b62ade908ffeb80e22f14edbe4c1ec04880bd30
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12304
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The Clang project has a powerful code rewrite engine in the form
of LibFormat. A auxiliary tool is provided called `clang-format'
that can take a coding style formalisation file and rewrite your
code to conform to this style. Further, a wrapper script called
`git-clang-format' is also provided that can hook pre-commits
potentially replacing our slow and poor coverage regexp scripts
on pre-commits.
Herein we provide essentially the Linux Style Guide formalism.
Change-Id: Ica2207fdb8a4702793fa73eba6293b7b36ea9050
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8036
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
All the deleted mainboard files contain no code besides some print
statements denoting, that the init is executed.
If such statements are desired, this should be done in common code so it
does not have to be added to each mainboard.
Therefore, also delete files with just print statements.
Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12355
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
