Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.
TEST=With CBI FW_CONFIG field set to 0x1561
localhost ~ # dmidecode -t 11
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: AUDIO-MAX98357_ALC5682I_I2S
String 2: CELLULAR-CELLULAR_PCIE
String 3: UFC-UFC_MIPI
String 4: WFC-WFC_MIPI
String 5: DB_SD-SD_GL9755S
Change-Id: I6cb35eb9c0fbe32764ca76bb7a929cc92fc38404
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70228
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NVMe is determined by a logical bit 1, not the physical SKU pin.
Thus, (logical) sku_id & 0x2 == 0x2 would mean that the device has
NVMe enabled on it. Previously, I thought that it was tied to a
physical pin, but this is not correct.
BUG=b:254281839
BRANCH=None
TEST=flash and boot on villager and make sure that NVMe is not
initialized in coreboot.
Change-Id: Iaa75d2418d6a2351d874842e8678bd6ad3c92526
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70230
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The devices in the list that was introduced in commit c66ea98577
("soc/intel/alderlake: provide a list of D-states to enter
LPM") are all internal. This CL skips the external buses (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)
BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents
Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required
for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using
8254 timer counter 2 output. However when 8254 timer is used, S0ix
will not work as 8254 has to be gated instead. For further info on
s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified
Checklist).
This CL also disables s0ix because it is not required by the
platform.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Galago Pro 6 (galp6) is an Alder Lake-P board.
Tested with a custom edk2 UefiPayloadPkg.
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- All USB ports
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.1
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.0.6
- Internal flashing with flashrom v1.2-1087-gde016a17
Not working:
- Detection of devices in TBT slot on boot
Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA
common code to skip sending CSE EOP cmd during finalize operation
rather uses boot state machine (either payload load or payload boot)
to delay in sending EOP cmd to CSE.
BUG=b:260041679
TEST=Able to boot to Google/Rex with this patch and observed ~150ms
savings in boot time
Without this patch:
942:before sending EOP to ME 1,795,702 (354)
943:after sending EOP to ME 1,950,526 (154,824)
With this patch:
942:before sending EOP to ME 2,051,406 (35,484)
943:after sending EOP to ME 2,057,583 (6,177)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows to send late EOP cmd to CSE (after CSE .final)
using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD)
if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config.
Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()`
to make the function name more meaningful with its operation.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.
Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors common code to allow cse_final() function to send
EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig.
This patch helps cse_final_ready_to_boot() and
cse_final_end_of_firmware() function for being meaningful with its
operation and let cse_final() being that outer layer to perform three
operations based on the selected kconfig.
1. send cse eop command
2. perform cse_final_ready_to_boot() operations
3. perform cse_final_end_of_firmware() operations
Additionally, ensures the platform that choose to send EOP late
(like JSL and TGL) is not being impacted due to this code refactoring
hence, skip calling into CSE.final if SoC selects
`SOC_INTEL_CSE_SEND_EOP_LATE` config.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I412291c9378011509d3825f9b01e81bfced53303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Presently, coreboot supports two instances of sending EOP cmd to
the Intel CSE.
1. Sending EOP cmd to CSE during `.final` operation from cse pci driver.
2. Starting with Alder Lake, the recommendation was to send EOP to CSE
earlier than CSE `.final` operation. Since then it's referred to as
`Sending EOP Early`. This method helped to save the CSE EOP
response time significantly.
During Meteor Lake platform, CSE EOP response time has become
non-deterministic and we have figured that sending EOP command later
than CSE .final operation is actually helping to optimize the boot time
significantly (around ~150ms savings compared to sending from `.final`
ops and ~5sec compared to sending CSE early).
Hence, this patch intended to create yet another kconfig for sending
CSE late (specifically after `.final` operation). The idea for this
newer config is to use the boot state machine for sending CSE EOP cmd.
The patch train in this series would add the specific changes to allow
sending EOP late and perform other essential operations required prior
booting to OS as coreboot decided to skip calling into FSP Notify phase.
Starting with Jasper Lake, coreboot sends EOP before loading payload
hence, this config is applicable for those platforms.
The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake
platform will select this newer config from SoC code.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patches for kconfig need to be in a format compatible with the quilt
tool, and usually also contain a header with some additional info like
the git commit. This header is in the same format as patches produced by
`git format-patch`, but the diff style git uses is incompatible with
quilt and there does not seem to be a straightforward way to format the
diff section to work.
Add some documentation for a method I found to go from a git commit to a
quilt compatible patch with git headers.
Change-Id: I7a8bbe41e0864be1d28116742b6b8b3fc440cc31
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch ensures dropping of the duplicate macro introduced with
'commit 9e4488ab06 ("soc/intel/{adl,cmn}: Add/Remove LTR
disqualification for UFS")'
`PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range
which can be used as is even in ufs.asl file.
BUG=b:252975357
TEST=Build and boot nirwen and see no issues in PLT runs.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Commit 2c102232e8 ("mb/amd/chausie,google/skyrim: increase
RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with
the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte
flash size, the amdfw part won't be placed on the expected position,
since the cbfs header is in that exact location and cbfstool places the
amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for
the non-chromeos builds to work around this.
TEST=Non-chromeos chausie build now boots and doesn't fail any more
before releasing the x86 cores from reset
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70133
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of using a fake lapic device hook up the cpu cluster to chip
cpu/intel/model_206ax.
The lapic device is also not needed as the mp init will allocate it for
the BSP at runtime.
Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The patch logs CSE RO's write protection information for Meteor Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.
Port of commit abe0d810f0 ("soc/intel/alderlake: Log CSE RO write
protection info for ADL").
BUG=none
TEST=Verify the write protection details on google/rex.
Excerpt from google/rex coreboot log:
[DEBUG] ME: WP for RO is enabled : YES
[DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
