Wrap bitfield structs in unions to reduce pointer usage. This adds more
uses of the `mei_dump()` function, only used for debugging. Refactoring
the MEI CSR functions to not use pointers is done in a follow-up.
Change-Id: I4defbb8c0e7812bf95c672ce529959f67c34537a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The RTC on Cezanne is an unstable wake source when the system is in
S0i3. We instead need to use an internal timer that triggers a GPIO that
acts as a wake source. This change provides the ACPI necessary to allow
the OS to manage the wake source.
BUG=b:209705576
TEST=Boot guybrush with this patch and several OS patches. Verified the
OS sets the correct wake bit, the system correctly suspends
and resumes, and the wake source is correctly accounted for.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We want ACPI to own the GPIOs. This will stop the GPIOs from being
exposed to the OS driver.
BUG=b:209705576, b:210694108
TEST=Dump ACPI table and verify GPIO are no longer in _CRS.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Use the `popcnt()` helper instead of manually counting the number of set
bits in the first `CONFIG_MAX_CPUS` bits with a loop. Also, use unsigned
types to store the number of active/total cores.
Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Setup eSPI to dedicated alert per the latest schematic changes.
DUT won't hang up at power on boot due to eSPI alert is triggerred
unexpectedly.
BUG=b:199458949,b:203446084
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
test power on/reboot on DUT (6 units) each 10 loops->pass
Change-Id: I55cda7a1af22e555a4f55285cb7e337a69e6c234
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Address Mode 0: Physical Address, bit 63~56: 0x00
Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40
Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80
Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0
It is the expanding mode for simple relative address mode, for which
address_mode equals 1.
Only mode 2 is added. We need to record current table base address and
calculate the offset. The ctx.current_table is zero outside the
table. When it goes into the function to integrate the table, it
should backup the old value and get current table base. Before it goes
out the function, it should restore the value.
If the table address mode is 2, the address in each entry should be
also add address mode information. If not, the address mode in entry
is meanless.
The old mode 0,1 should be back compatible.
Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Preloading files before vboot runs and using them after vboot has
finished will result in the wrong files getting used. Disable
cbfs_preload to avoid this behavior.
BUG=b:179699789
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7698b481a73fb24eecf4c810ff8be8b6826528ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change consolidates the COOP rules. Co-op in theory works in all
x86 stages now, but it hasn't been enabled yet.
BUG=b:179699789
TEST=Boot guybrush to OS and verify preloads still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1197406d1d36391998b08e3076146bb2fff59d00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch adds the following list of changes:
1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p
devictree.
2. Add support for 2 mainboards as ADL-N board with default EC (Windows
SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from
adlrvp-p.
3. Add mainboard Kconfig to Kconfig.name file
4. Handle mainboard names in Kconfig file for ADLRVP N
5. Add config options to pick the adlrvp_n devicetree
Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the
first generation of PSP mailbox interface and not on the second
generation. The second generation of the PSP mailbox interface was
introduced with the AMD family 17h SoCs on which the DRAM is already
initialized before the x86 cores are released from reset.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
In the case of deduct_cmd_len being set and the adjusted cmd_len >=
ctrlr_max, ctrlr_max wasn't being adjusted and still had the value of
ctrlr->max_xfer_size. Handle this edge case (which we should never run
into) by setting ctrlr_max to 0 and printing a warning to the console.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9941b2947bb0a44dfae8ee69f509795dfb0cb241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined
compared to the previous generations. It is unclear if adding some
special handling for Cezanne would be worth the effort, since the
current code just doesn't use the last byte which should be safe to do,
since this only affects the maximum number of bytes that can be used for
one SPI transaction. Having another byte to use on Cezanne wouldn't
reduce the number of SPI transactions to write a 256 byte data block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of
the SPI controller's MMIO region for Stoneyridge and Picasso. Both
SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended
up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH
isn't changed.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause
the TPM kernel driver to send a shutdown command before s0i3 entry. This
change depends on S0i3 verstage running and reinitializing the TPM.
BUG=b:200578885
BRANCH=None
TEST=TPM shutdown sent during s0i3 entry on guybrush
Change-Id: I206022cc2a29690186206966c5d45bd55c303248
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add new memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Micron MT53E512M32D1NP-046 WT:B
2. Samsung K4U6E3S4AB-MGCL
3. Hynix H54G46CYRBX267
BUG=b:209889645
BRANCH=dedede
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I0b2f447a610a0a857e819ede257ac89cfd817018
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59991
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial gpio configuration for taniks according to schematics
G570_MB_CHROME_1207_1630_ADC. The schematics reserved HPS and FP but
taniks doesn't use them, so set FP and HPS related pins to NC.
BUG=b:209492408, b:209553289
TEST=FW_NAME=taniks emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
