drivers/gfx/nvidia: acpi: Skeleton code for NBCI

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I5fbc8e1480670457586885c6099c19d73ca06c45

.checkpatch.conf

@@ -22,7 +22,6 @@
 --ignore PRINTK_WITHOUT_KERN_LEVEL
 --ignore ASSIGN_IN_IF
 --ignore UNNECESSARY_ELSE
---ignore GERRIT_CHANGE_ID
 
 # FILE_PATH_CHANGES seems to not be working correctly. It will
 # choke on added / deleted files even if the MAINTAINERS file

.gitmodules

@@ -48,7 +48,6 @@
 	path = 3rdparty/cmocka
 	url = https://review.coreboot.org/cmocka.git
 	update = none
-	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
 	url = https://review.coreboot.org/qc_blobs.git

.mailmap

@@ -1,425 +0,0 @@
-# Map author and committer names and email addresses to canonical real names and
-# email addresses. https://git-scm.com/docs/gitmailmap
-#
-# Note that this is only needed in the case where someone has contributed
-# with multiple different email addresses or Names.
-#
-# Forms: Proper Name <commit@email.xx>
-#        Proper Name <proper@email.xx> <commit@email.xx>
-#        Proper Name <proper@email.xx> Commit Name <commit@email.xx>
-
-
-Aamir Bohra <aamirbohra@gmail.com> <aamir.bohra@intel.com>
-Aaron Durbin <adurbin@chromium.org>
-Aaron Durbin <adurbin@chromium.org> <adurbin@adurbin.bld.corp.google.com>
-Aaron Durbin <adurbin@chromium.org> <adurbin@google.com>
-Abhay Kumar <abhay.kumar@intel.com>
-Abhinav Hardikar <realdevmaster64@gmail.com> devmaster64 <devmaster64@gmail.com>
-Alex Levin <levinale@google.com> <levinale@chromium.org>
-Alex Miao <alex.miao@mediatek.corp-partner.google.com>
-Alexandru Gagniuc <mr.nuke.me@gmail.com> <alexandrux.gagniuc@intel.com>
-Alexandru Gagniuc <mr.nuke.me@gmail.com> mrnuke <mrnuke@nukelap.gtech>
-Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
-Amol N Sukerkar <amol.n.sukerkar@intel.com>
-Andrea Barberio <barberio@fb.com> <insomniac@slackware.it>
-Andrey Petrov <anpetrov@fb.com> <andrey.petrov@intel.com>
-Andrey Pronin <apronin@chromium.org> <apronin@google.com>
-Andriy Gapon <avg@FreeBSD.org> <avg@icyb.net.ua>
-Anil Kumar <anil.kumar.k@intel.com> <anil.kumar.k@intel.corp-partner.google.com>
-Anish K. Patel <anishp@win-ent.com>
-Anton Kochkov <anton.kochkov@gmail.com> <a.kochkov@securitycode.ru>
-Antonello Dettori <dev@dettori.io> <dettori.an@gmail.com>
-Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
-Arne Georg Gleditsch <arne.gleditsch@numascale.com> <arne.gleditsch@numscale.com>
-Asami Doi <d0iasm.pub@gmail.com> <doiasami1219@gmail.com>
-Ashwin Kumar <ashk@codeaurora.org>
-Axel Holewa <mono@posteo.de> Mono <mono-for-coreboot@donderklumpen.de>
-Axel Holewa <mono@posteo.de> Mono <mono@posteo.de>
-Bao Zheng <fishbaozi@gmail.com>
-Bao Zheng <fishbaozi@gmail.com> <Zheng Bao zheng.bao@amd.com>
-Bao Zheng <fishbaozi@gmail.com> <zheng.bao@amd.com>
-Bayi Cheng <bayi.cheng@mediatek.com>
-Ben Zhang <benzh@google.com> <benzh@chromium.org>
-Bernhard M. Wiedermann <corebootbmw@lsmod.de>
-Bill Xie <persmule@hardenedlinux.org> <persmule@gmail.com>
-Bill Xie <persmule@hardenedlinux.org> Bill XIE <persmule@hardenedlinux.org>
-Bingxun Shi <bingxunshi@gmail.com>
-Bingxun Shi <bingxunshi@gmail.com> <bxshi@msik.com.cn>
-Brandon Breitenstein <brandon.breitenstein@intel.com> <brandon.breitenstein@intel.corp-partner.google.com>
-Bruce Griffith <bruce.griffith@se-eng.com> <Bruce.Griffith@se-eng.com>
-Bryant Ou <Bryant.Ou.Q@gmail.com>
-Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> <Carl-Daniel Hailfinger>
-Casper Chang<casper_chang@wistron.corp-partner.google.com> <casper.chang@bitland.corp-partner.google.com>
-Caveh Jalali <caveh@chromium.org> <caveh@google.com>
-Caveh Jalali <caveh@chromium.org> caveh jalali <caveh@chromium.org>
-Charles Marslett <charles@scarlettechnologies.com> <charles.marslett@silverbackltd.com>
-Chee Soon Lew <chee.soon.lew@intel.com>
-Cheng-Yi Chiang <cychiang@chromium.org> <cychiang@google.com>
-Chris Ching <chris@ching.codes> <chingcodes@chromium.org>
-Chris Ching <chris@ching.codes> <chingcodes@google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> <chriswang@ami.corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> Chris Wang <chris.wang@amd-corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> chris wang <chris.wang@amd.corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> Chris.Wang <chris.wang@amd.corp-partner.google.com>
-Chris Zhou <chris_zhou@compal.corp-partner.google.com>
-Christian Ruppert <idl0r@qasl.de> <idl0r@gentoo.org>
-Chun-Jie Chen <chun-jie.chen@mediatek.corp-partner.google.com>
-Clay Daniels Jr <clay.daniels.jr@gmail.com>
-Cole Nelson<colex.nelson@intel.com>
-Corey Osgood <corey.osgod@gmail.com> <corey_osgood@verizon.net>
-Corey Osgood <corey.osgod@gmail.com> <corey.osgood@gmail.com>
-Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
-Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
-Da Lao <dalao@tutanota.com> dalao <dalao@tutanota.com>
-Daisuke Nojiri <dnojiri@chromium.org> dnojiri <dnojiri@chromium.org>
-Dan Elkouby <streetwalkermc@gmail.com> <streetwalrus@codewalr.us>
-Daphne Jansen <dcjansen@chromium.org> Justin TerAvest <teravest@chromium.org>
-Daphne Jansen <dcjansen@chromium.org> Justin TerAvest <teravest@google.com>
-Dave Parker <dparker@chromium.org>
-David Hendricks <davidhendricks@gmail.com> <david.hendricks@gmail.com>
-David Hendricks <davidhendricks@gmail.com> <dhendricks@fb.com>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@chromium.org>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@fb.com>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@google.com>
-David Hendricks <davidhendricks@gmail.com> David W. Hendricks <dwh@lanl.gov>
-David Wu <david_wu@quantatw.com> <david_wu@quanta.corp-partner.google.com>
-David Wu <david_wu@quantatw.com> david <david_wu@quantatw.com>
-Dawei Chien <dawei.chien@mediatek.com>
-Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> <GNUtoo@no-log.org>
-Derek Huang <derek.huang@intel.com> <derek.huang@intel.corp-partner.google.com>
-Dmitry Ponamorev <dponamorev@gmail.com>
-Douglas Anderson <dianders@chromium.org>
-Duncan Laurie <dlaurie@chromium.org> <dlaurie@google.com>
-Ed Swierk <eswierk@aristanetworks.com> <eswierk@arastra.com>
-Edward O'Callaghan <quasisec@google.com> <edward.ocallaghan@koparo.com>
-Edward O'Callaghan <quasisec@google.com> <eocallaghan@alterapraxis.com>
-Edward O'Callaghan <quasisec@google.com> <funfunctor@folklore1984.net>
-Edward O'Callaghan <quasisec@google.com> <quasisec@chromium.org>
-Eric Biederman <ebiederm@xmission.com> <ebiederman@lnxi.com>
-Eric Biederman <ebiederm@xmission.com> Eric W. Biederman <ebiederm@xmission.com>
-Eugene Myers <edmyers@tycho.nsa.gov> <cedarhouse@comcast.net>
-Evgeny Zinoviev <me@ch1p.io> <me@ch1p.com>
-Felix Durairaj <felixx.durairaj@intel.com>
-Felix Held <felix-coreboot@felixheld.de> <felix-github@felixheld.de>
-Felix Held <felix-coreboot@felixheld.de> <felix.held@amd.corp-partner.google.com>
-Felix Singer <felixsinger@posteo.net> <felix.singer@9elements.com>
-Felix Singer <felixsinger@posteo.net> <felix.singer@secunet.com>
-Felix Singer <felixsinger@posteo.net> <migy@darmstadt.ccc.de>
-Francois Toguo Fotso <francois.toguo.fotso@intel.com> Francois Toguo <francois.toguo.fotso@intel.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com> Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com> FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
-Frank Vibrans <efdesign98@gmail.com> efdesign98 <efdesign98@gmail.com>
-Frank Vibrans <efdesign98@gmail.com> Frank Vibrans <frank.vibrans@amd.com>
-Frank Vibrans <efdesign98@gmail.com> frank vibrans <frank.vibrans@scarletltd.com>
-Frank Vibrans <efdesign98@gmail.com> Frank Vibrans <frank.vibrans@se-eng.com>
-Frank Vibrans <efdesign98@gmail.com> Frank.Vibrans <frank.vibrans@amd.com>
-Furquan Shaikh <furquan@chromium.org> <furquan@google.com>
-G. Pangao <gtk_pangao@mediatek.com> <gtk_pangao@mediatek.corp-partner.google.com>
-Gabe Black <gabeblack@chromium.org> <gabeblack@chromium.com>
-Gabe Black <gabeblack@chromium.org> <gabeblack@google.com>
-Gaggery Tsai <gaggery.tsai@intel.com>
-Georg Wicherski <gwicherski@gmail.com> <gw@oxff.net>
-Gomathi Kumar <gomathi.kumar@intel.com>
-Greg V <greg@unrelenting.technology>
-Greg Watson <gwatson@lanl.gov> <jarrah@users.sourceforge.net>
-Hannah Williams <hannah.williams@dell.com> <hannah.williams@intel.com>
-Hao Chou <hao_chou@pegatron.corp-partner.google.com>
-Haridhar Kalvala <haridhar.kalvala@intel.com> haridhar <haridhar.kalvala@intel.com>
-Harsha Priya <harshapriya.n@intel.com>
-Harsha Priya <harshapriya.n@intel.com> <harhapriya.n@intel.com>
-Harshit Sharma <harshitsharmajs@gmail.com> harshit <harshitsharmajs@gmail.com>
-Henry C Chen <henryc.chen@mediatek.com> henryc.chen <henryc.chen@mediatek.com>
-Himanshu Sahdev <sahdev.himan@gmail.com> <himanshusah@hcl.com>
-Himanshu Sahdev <sahdev.himan@gmail.com> Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com>
-Hsuan Ting Chen <roccochen@chromium.org> Hsuan-ting Chen <roccochen@google.com>
-Huang Lin <hl@rock-chips.com>
-Huayang Duan <huayang.duan@mediatek.com>
-Huki Huang <huki.huang@intel.com>
-Idwer Vollering <vidwer@gmail.com> <idwer_v@hotmail.com>
-Igor Bagnucki <bagnucki02@gmail.com> <igor.bagnucki@3mdeb.com>
-Indrek Kruusa <indrek.kruusa@artecdesign.ee>  <Indrek Kruusa>
-Ivy Jian <ivy_jian@compal.com> <ivy_jian@compal.corp-partner.google.com>
-Jacob Laska <jlaska91@gmail.com> <jlaska@xes-inc.com>
-Jakub Czapiga <jacz@semihalf.com>
-Jason Wang <Qingpei.Wang@amd.com> Jason WangQingpei.wang <Jason WangQingpei.wang@amd.com>
-JasonX Z Chen <jasonx.z.chen@intel.com>
-Jens Kühnel <coreboot@jens.kuehnel.org> Jens Kuehnel <coreboot@jens.kuehnel.org>
-Jens Rottmann <JRottmann@LiPPERTembedded.de> <JRottmann@LiPPERTEmbedded.de>
-Jeremy Compostella  <jeremy.compostella@intel.com> <jeremy.compostella@gmail.com>
-Jeremy Soller <jackpot51@gmail.com> <jeremy@system76.com>
-Jiaxin Yu <jiaxin.yu@mediatek.com>
-Jiazi Yang <Tomato_Yang@asus.com>
-Jim Lai <jim.lai@intel.com>
-Jingle Hsu <jingle_hsu@wiwynn.com>
-Jinkun Hong <jinkun.hong@rock-chips.com>
-Joe Moore <awokd@danwin1210.me>
-Joe Pillow <joseph.a.pillow@gmail.com>
-Johanna Schander <coreboot@mimoja.de>
-John Zhao <john.zhao@intel.com>
-Jonathan Kollasch <jakllsch@kollasch.net>
-Jordan Crouse <jordan@cosmicpenguin.net>  <Jordan Crouse>
-Jordan Crouse <jordan@cosmicpenguin.net> <jordan.crouse@amd.com>
-Josef Kellermann <Joseph.Kellermann@heitec.de> <seppk@arcor.de>
-Josef Kellermann <Joseph.Kellermann@heitec.de> Josef Kellermannseppk <Josef Kellermannseppk@arcor.de>
-Joseph Smith <joe@settoplinux.org> <joe@settoplinux.org Acked-by: Joseph Smith joe@settoplinux.org>
-Joseph Smith <joe@settoplinux.org> <joe@smittys.pointclark.net>
-Juergen Beisert <juergen@kreuzholzen.de> <juergen127@kreuzholzen.de>
-Julian Schroeder <julianmarcusschroeder@gmail.com> <julian.schroeder@amd.com>
-Julien Viard de Galbert <julien@vdg.name> <jviarddegalbert@online.net>
-Justin Wu <amersel@runbox.me>
-Kaiyen Chang <kaiyen.chang@intel.com> <kaiyen.chang@intel.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> <kane.chen@intel.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> Kane Chenffd <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> kane_chen <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
-Karthikeyan Ramasubramanian <kramasub@google.com> <kramasub@chromium.org>
-Katie Roberts-Hoffman <katierh@chromium.org>  <katierh@google.com>
-Kerry She <kerry.she@amd.com> <Kerry.she@amd.com>
-Kerry Sheh <shekairui@gmail.com>
-Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <kevin.chiu@quanta.corp-partner.google.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <kevin.chiu@quantatw.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <Kevin.Chiu@quantatw.com>
-Kevin Paul Herbert <kph@platinasystems.com> <kevin@trippers.org>
-Kevin Paul Herbert <kph@platinasystems.com> <kph@meraki.net>
-Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> kirk_wang <kirk_wang@pegatron.corp-partner.google.com>
-Konstantin Aladyshev <aladyshev22@gmail.com> <aladyshev@nicevt.ru>
-Kyösti Mälkki <kyosti.malkki@gmail.com>
-Kyösti Mälkki <kyosti.malkki@gmail.com> <kyosti.malkki@3mdeb.com>
-Lean Sheng Tan <sheng.tan@9elements.com> <lean.sheng.tan@intel.com>
-Lee Leahy <lpleahyjr@gmail.com> <leroy.p.leahy@intel.com>
-Li Cheng Sooi <li.cheng.sooi@intel.com>
-Lijian Zhao <lijian.zhao@intel.com>
-Lin Huang <hl@rock-chips.com>
-Maciej Matuszczyk <maccraft123mc@gmail.com>
-Maggie Li <maggie.li@amd.com> <Maggie.li@amd.com>
-Manideep Kurumella <mkurumel@qualcomm.corp-partner.google.com> <mkurumel@codeaurora.org>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@amd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@gmail.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@scarletltd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@se-eng.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj.jones@amd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj303@gmail.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj303@yahoo.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcjones@sysproconsulting.com>
-Marc Jones <marc@marcjonesconsulting.com> Marc Jones (marc.jones <Marc Jones (marc.jones@amd.com)>
-Marc Jones <marc@marcjonesconsulting.com> Marc Jones(marc.jones <Marc Jones(marc.jones@amd.com)>
-Marcello Sylvester Bauer <sylv@sylv.io>
-Marcello Sylvester Bauer <sylv@sylv.io> <info@marcellobauer.com>
-Marcello Sylvester Bauer <sylv@sylv.io> <sylvblck@sylv.io>
-Marco Chen <marcochen@google.com> <marcochen@chromium.org>
-Mariusz Szafrański <mariuszx.szafranski@intel.com> Mariusz Szafranski <mariuszx.szafranski@intel.com>
-Marshall Dawson <marshalldawson3rd@gmail.com> <marshall.dawson@amd.corp-partner.google.com>
-Marshall Dawson <marshalldawson3rd@gmail.com> <marshall.dawson@scarletltd.com>
-Mart Raudsepp <leio@gentoo.org> <mart.raudsepp@artecdesign.ee>
-Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
-Martin Roth <gaumless@gmail.com> <martin.roth@se-eng.com>
-Martin Roth <gaumless@gmail.com> <martin@coreboot.org>
-Martin Roth <gaumless@gmail.com> <martinr@coreboot.org>
-Martin Roth <gaumless@gmail.com> <martinroth@chromium.org>
-Martin Roth <gaumless@gmail.com> <martinroth@google.com>
-Martin Roth <gaumless@gmail.com> Martin Roth <martin@se-eng.com>
-Marx Wang <marx.wang@intel.com>
-Mathias Krause <minipli@googlemail.com> <mathias.krause@secunet.com>
-Mathias Krause <minipli@googlemail.com> <Mathias.Krause@secunet.com>
-Mats Erik Andersson <mats.andersson@gisladisker.org> <mats.andersson@gisladisker.se>
-Matt DeVillier <matt.devillier@gmail.com> <matt.devillier@puri.sm>
-Matt Papageorge <matthewpapa07@gmail.com> <matt.papageorge@amd.corp-partner.google.com>
-Matt Ziegelbaum <ziegs@google.com> <ziegs@chromium.org>
-Maulik V Vaghela <maulik.v.vaghela@intel.com>
-Maulik V Vaghela <maulik.v.vaghela@intel.com> <maulik.v.vaghela@intel.corp-partner.google.com>
-Max Blau <tripleshiftone@gmail.com> Bluemax <1403092+BlueMax@users.noreply.github.com>
-Maxim Polyakov <max.senia.poliak@gmail.com> <m.poliakov@yahoo.com>
-Mengqi Zhang <Mengqi.Zhang@mediatek.com> mengqi.zhang <mengqi.zhang@mediatek.com>
-Michael Niewöhner <foss@mniewoehner.de> <michael.niewoehner@8com.de>
-Michael Xie <Michael.Xie@amd.com> <Michael Xie Michael.Xie@amd.com>
-Michele Guerini Rocco <rnhmjoj@inventati.org>
-Mike Banon <mikebdp2@gmail.com> <mike.banon@3mdeb.com>
-Mike Hsieh <Mike_Hsieh@wistron.com> <mike_hsieh@wistron.corp-partner.google.com>
-Mike Loptien <loptienm@gmail.com> <mike.loptien@se-eng.com>
-Mondrian Nuessle <nuessle@uni-hd.de>
-Mondrian Nuessle <nuessle@uni-hd.de> <nuessle@uni-mannheim.de>
-Motiejus Jakštys <desired.mta@gmail.com>
-Myles Watson <mylesgw@gmail.com>  <myles@pel.cs.byu.edu>
-Nancy Lin <nancy.lin@mediatek.com>
-Naresh Solanki <naresh.solanki@intel.com>
-Naresh Solanki <naresh.solanki@intel.com> <Naresh.Solanki@intel.com>
-Naveen Manohar <naveen.m@intel.com>
-Naveen Manohar <naveen.m@intel.com>
-Neil Chen <neilc@nvidia.com> <neilc%nvidia.com@gtempaccount.com>
-Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
-Nick Vaccaro <nvaccaro@google.com> <nvaccaro@chromium.org>
-Nicky Sielicki <nlsielicki@wisc.edu>
-Nico Huber <nico.h@gmx.de> <nico.huber@secunet.com>
-Nicolas Boichat <drinkcat@chromium.org> <drinkcat@google.com>
-Nicolas Reinecke <nr@das-labor.org>
-Nils Jacobs <njacobs8@adsltotaal.nl> <njacobs8@hetnet.nl>
-Nina Wu <nina-cm.wu@mediatek.com> <nina-cm.wu@mediatek.corp-partner.google.com>
-Oskar Enoksson <enok@lysator.liu.se>
-Oskar Enoksson <enok@lysator.liu.se> <oskeno@foi.se>
-Pablo Moyano <42.pablo.ms@gmail.com> p4block <p4block@users.noreply.github.com>
-Patrick Georgi <patrick@coreboot.org> <Patrick Georgi patrick.georgi@coresystems.de>
-Patrick Georgi <patrick@coreboot.org> <Patrick Georgi patrick@georgi-clan.de>
-Patrick Georgi <patrick@coreboot.org> <patrick.georgi@coresystems.de>
-Patrick Georgi <patrick@coreboot.org> <patrick.georgi@secunet.com>
-Patrick Georgi <patrick@coreboot.org> <Patrick.Georgi@secunet.com>
-Patrick Georgi <patrick@coreboot.org> <patrick@georgi-clan.de>
-Patrick Georgi <patrick@coreboot.org> <patrick@georgi.software>
-Patrick Georgi <patrick@coreboot.org> Patrick Georgi <pgeorgi@chromium.org>
-Patrick Georgi <patrick@coreboot.org> Patrick Georgi <pgeorgi@google.com>
-Patrick Rudolph  <siro@das-labor.org> <patrick.rudolph@9elements.com>
-Paul Fagerburg <pfagerburg@chromium.org> <pfagerburg@google.com>
-Paul Kocialkowski <contact@paulk.fr>
-Paul Ma <magf@bitland.com.cn> <magf@bitland.corp-partner.google.com>
-Paul Ma <magf@bitland.com.cn> Magf - <magf@bitland.corp-partner.google.com>
-Paul Menzel <pmenzel@molgen.mpg.de> <paulepanter@mailbox.org>
-Paul Menzel <pmenzel@molgen.mpg.de> <paulepanter@users.sourceforge.net>
-Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
-Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
-Philip Chen <philipchen@google.com>
-Philip Chen <philipchen@google.com> <philipchen@chromium.org>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com> <philipp.deppenwiese@9elements.com>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com> <zaolin@das-labor.org>
-Ping-chung Chen <ping-chung.chen@intel.com>
-Ping-chung Chen <ping-chung.chen@intel.com>
-Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> <piotr.kleins@gmail.com>
-Piotr Szymaniak <szarpaj@grubelek.pl>
-Po Xu <jg_poxu@mediatek.com>
-Po Xu <jg_poxu@mediatek.com> <jg_poxu@mediatek.corp-partner.google.com>
-Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
-Preetham Chandrian <preetham.chandrian@intel.com>
-Puthikorn Voravootivat <puthik@chromium.org> <puthik@google.com>
-QingPei Wang <wangqingpei@gmail.com>
-Quan Tran <qeed.quan@gmail.com>
-Rasheed Hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
-Raul Rangel <rrangel@chromium.org>
-Ravi Kumar Bokka <rbokka@codeaurora.org>
-Ravindra <ravindra@intel.com>
-Ravindra <ravindra@intel.com> Ravindra N <ravindra@intel.corp-partner.google.com>
-Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
-Raymond Chung <raymondchung@ami.corp-partner.google.com>
-Raymond Danks <raymonddanks@gmail.com> <ray.danks@se-eng.com>
-Reka Norman <rekanorman@google.com> <rekanorman@chromium.org>
-Ren Kuo <ren.kuo@quantatw.com>
-Ren Kuo <ren.kuo@quantatw.com> <ren.kuo@quanta.corp-partner.google.com>
-Rex-BC Chen <rex-bc.chen@mediatek.com> <rex-bc.chen@mediatek.corp-partner.google.com>
-Ricardo Ribalda <ribalda@chromium.org> <ricardo.ribalda@gmail.com>
-Richard Spiegel <richard.spiegel@silverbackltd.com> <richard.spiegel@amd.corp-partner.google.com>
-Rishavnath Satapathy <rishavnath.satapathy@intel.com>
-Ritul Guru <ritul.bits@gmail.com>
-Rizwan Qureshi <rizwan.qureshi@intel.com> <rizwan.qureshi@intel.corp-partner.google.com>
-Robbie Zhang <robbie.zhang@intel.com>
-Robert Chen <robert.chen@quanta.corp-partner.google.com>
-Robert Chen <robert.chen@quanta.corp-partner.google.com> = <robert.chen@quanta.corp-partner.google.com>
-Roger Pau Monne <roger.pau@citrix.com>
-Roman Kononov <kononov@dls.net> <kononov195-lbl@yahoo.com>
-Ron Minnich <rminnich@gmail.com>
-Ron Minnich <rminnich@gmail.com> <Ron Minnich>
-Ron Minnich <rminnich@gmail.com> <Ronald G. Minnich rminnich@gmail.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <minnich@google.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@chromium.org>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@google.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@lanl.gov>
-Ron Minnich <rminnich@gmail.com> ronald g. minnich <ronald g. minnich>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <Ronald G. Minnich>
-Ronak Kanabar <ronak.kanabar@intel.com>
-Rudolf Marek <r.marek@assembler.cz> <r.marek@asssembler.cz>
-Ryan Chuang <ryan.chuang@mediatek.com> <ryan.chuang@mediatek.corp-partner.google.com>
-Santhosh Janardhana Hassan <sahassan@google.com>
-Scott Chao <scott_chao@wistron.corp-partner.google.com> <scott.chao@bitland.corp-partner.google.com>
-Scott Duplichan <scott@notabs.org> <sc...@notabs.org>
-Scott Tsai <AT>
-Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
-Selma Bensaid <selma.bensaid@intel.com>
-Seunghwan Kim <sh_.kim@samsung.com>
-Seunghwan Kim <sh_.kim@samsung.com> <sh_.kim@samsung.corp-partner.google.com>
-Seunghwan Kim <sh_.kim@samsung.com> sh.kim <sh_.kim@samsung.corp-partner.google.com>
-Shawn Chang <citypw@gmail.com>
-Shawn Nematbakhsh <shawnn@google.com> <shawnn@chromium.org>
-Shelley Chen <shchen@google.com> <shchen@chromium.org>
-Sheng-Liang Pan <Sheng-Liang.Pan@quantatw.com> <sheng-liang.pan@quanta.corp-partner.google.com>
-Shreesh Chhabbi <shreesh.chhabbi@intel.com> <shreesh.chhabbi@intel.corp-partner.google.com>
-Shunqian Zheng <zhengsq@rock-chips.com>
-Siyuan Wang <wangsiyuanbuaa@gmail.com>
-Sowmya <v.sowmya@intel.com>
-Sridhar Siricilla <sridhar.siricilla@intel.com>
-Sridhar Siricilla <sridhar.siricilla@intel.com> <sridhar.siricilla@intel.corp-partner.google.com>
-Srinidhi Kaushik <srinidhi.n.kaushik@intel.com>
-Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
-Stefan Ott <stefan@ott.net> <coreboot@desire.ch>
-Stefan Reinauer <stepan@coreboot.org> <reinauer@chromium.org>
-Stefan Reinauer <stepan@coreboot.org> <reinauer@google.com>
-Stefan Reinauer <stepan@coreboot.org> <Stefan Reinauerstepan@coresystems.de>
-Stefan Reinauer <stepan@coreboot.org> <stefan.reinauer@coreboot.org>
-Stefan Reinauer <stepan@coreboot.org> <stepan@coresystems.de>
-Stefan Reinauer <stepan@coreboot.org> <stepan@openbios.org>
-Stephan Guilloux <stephan.guilloux@free.fr> <mailto:stephan.guilloux@free.fr>
-Subrata Banik <subratabanik@google.com> <subi.banik@gmail.com>
-Subrata Banik <subratabanik@google.com> <subrata.banik@intel.com>
-Subrata Banik <subratabanik@google.com> <subrata.banik@intel.com>
-Sudheer Kumar Amrabadi <samrab@codeaurora.org>
-Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
-Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
-Susendra Selvaraj <susendra.selvaraj@intel.com>
-Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
-T Michael Turney <mturney@codeaurora.org> mturney mturney <quic_mturney@quicinc.com>
-T Michael Turney <mturney@codeaurora.org> T Michael Turney <quic_mturney@quicinc.com>
-T.H. Lin <T.H_Lin@quantatw.com> <t.h_lin@quanta.corp-partner.google.com>
-T.H. Lin <T.H_Lin@quantatw.com> T.H.Lin <T.H_Lin@quantatw.com>
-Taniya Das <quic_tdas@quicinc.com> <tdas@codeaurora.org>
-Tao Xia <xiatao5@huaqin.corp-partner.google.com>
-Thejaswani Putta  <thejaswani.putta@intel.com> <thejaswani.putta@intel.corp-partner.google.com>
-Thejaswani Putta <thejaswani.putta@intel.com>
-Thejaswani Putta <thejaswani.putta@intel.com> Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com>
-Thomas Heijligen <thomas.heijligen@secunet.com> <src@posteo.de>
-Tim Chen <Tim-Chen@quantatw.com> <tim-chen@quanta.corp-partner.google.com>
-Tim Chu <Tim.Chu@quantatw.com>
-Tim Wawrzynczak <twawrzynczak@chromium.org> <twawrzynczak@google.com>
-Timothy Pearson <tpearson@raptorengineering.com> <tpearson@raptorengineeringinc.com>
-Tinghan Shen <tinghan.shen@mediatek.com>
-Tobias Diedrich <ranma+coreboot@tdiedrich.de> <ranma+openocd@tdiedrich.de>
-Tracy Wu <tracy.wu@intel.com> <tracy.wu@intel.corp-partner.google.com>
-Tristan Corrick <tristan@corrick.kiwi> <tristancorrick86@gmail.com>
-Tyler Wang <tyler.wang@quanta.corp-partner.google.com> <Tyler.Wang@quanta.corp-partner.google.com>
-Usha P <usha.p@intel.com> <usha.p@intel.corp-partner.google.com>
-V Sujith Kumar Reddy <vsujithk@codeaurora.org>
-Vadim Bendebury <vbendeb@chromium.org> <vbendeb@google.com>
-Vaibhav Shankar <vaibhav.shankar@intel.com>
-Van Chen <van_chen@compal.corp-partner.google.com>
-Varshit Pandya <varshit.b.pandya@intel.com>
-Varshit Pandya <varshit.b.pandya@intel.com> Varshit B Pandya <varshit.b.pandya@intel.com>
-Varun Joshi <varun.joshi@intel.com> <varun.joshi@intel.corp-partner.google.com>
-Vincent Lim <vincent.lim@amd.com>  <Vincent Lim vincent.lim@amd.com>
-Vladimir Serbinenko <phcoder@gmail.com>
-Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> <Wayne3_Wang@pegatron.corp-partner.google.com>
-William Wu <wulf@rock-chips.com>
-Wim Vervoorn <wvervoorn@eltan.com>
-Wisley Chen <wisley.chen@quantatw.com>
-Wisley Chen <wisley.chen@quantatw.com> <wisley.chen@quanta.corp-partner.google.com>
-Xi Chen <xixi.chen@mediatek.com> <xixi.chen@mediatek.corp-partner.google.com>
-Xiang Wang <merle@hardenedlinux.org> <wxjstz@126.com>
-Xingyu Wu <wuxy@bitland.corp-partner.google.com>
-Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
-Yang A Fang <yang.a.fang@intel.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai.lu at amd.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai.lu@amd.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai@kernel.org>
-Yongkun Yu <yuyongkun@huaqin.corp-partner.google.com>
-Yongqiang Niu <yongqiang.niu@mediatek.com>
-Youness Alaoui <snifikino@gmail.com> <kakaroto@kakaroto.homelinux.net>
-Youness Alaoui <snifikino@gmail.com> <youness.alaoui@puri.sm>
-Yu-Hsuan Hsu <yuhsuan@google.com>
-Yu-Hsuan Hsu <yuhsuan@google.com> <yuhsuan@chromium.org>
-Yu-Ping Wu <yupingso@google.com> <yupingso@chromium.org>
-Yuanlidingm <yuanliding@huaqin.corp-partner.google.com>
-Yuchen Huang <yuchen.huang@mediatek.com> <yuchen.huang@mediatek.corp-partner.google.com>
-Yuji Sasaki <sasakiy@chromium.org> <sasakiy@google.com>
-Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
-Zhi Li <lizhi7@huaqin.corp-partner.google.com>
-Zhongze Hu <frankhu@chromium.org> <frankhu@google.com>
-Zhuo-Hao Lee <zhuo-hao.lee@intel.com>
-Zhuohao Lee <zhuohao@chromium.org> <zhuohao@google.com>

Documentation/arch/x86/index.md

@@ -26,7 +26,9 @@ In order to add support for x86_64 the following assumptions were made:
 * A stage can install new page tables in RAM
 
 ## Page tables
-A `pagetables` cbfs file is generated based on an assembly file.
+Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes
+the page tables to a file which is then included into the CBFS as file called
+`pagetables`.
 
 To generate the static page tables it must know the physical address where to
 place the file.

Documentation/community/code_of_conduct.md

@@ -115,4 +115,4 @@ Our arbitration team consists of the following people
 This Code of Conduct is distributed under
 a [Creative Commons Attribution-ShareAlike
 license](http://creativecommons.org/licenses/by-sa/3.0/).  It is based
-on the [Citizen Code of Conduct](https://web.archive.org/web/20200330154000/http://citizencodeofconduct.org/)
+on the [Citizen Code of Conduct](http://citizencodeofconduct.org/)

Documentation/community/conferences.md

@@ -14,7 +14,7 @@ their development kit with them and conduct development sessions.
 
 [Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_facebook/)  by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebook.mp4)) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf)) (2019-02-03)
 
-[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://web.archive.org/web/20211027210118/https://events.ccc.de/congress/2018/wiki/index.php/Main_Page)
+[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://events.ccc.de/congress/2018)
 ([slides](https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9778-deu-eng-Open_Source_Firmware_hd-slides.mp4)) (2018-12-27)
 
 [coreboot mainboard porting with Intel FSP 2.0](https://www.youtube.com/watch?v=qUgo-AVsSCI) by Subrata Banik at OSFC 2018

Documentation/community/index.md

@@ -1,6 +0,0 @@
-# Community
-
-* [Code of Conduct](code_of_conduct.md)
-* [Language style](language_style.md)
-* [Community forums](forums.md)
-* [coreboot at conferences](conferences.md)

Documentation/community/services.md

@@ -1,6 +1,6 @@
 # Accounts on coreboot.org
 
-There are a number of places where you can benefit from creating an account
+There are a number of places where you can benefit from creaating an account
 in our community. Since there is no single sign-on system in place (at this
 time), they come with their own setup routines.
 

Documentation/contributing/coding_style.md

@@ -960,55 +960,17 @@ asm ("magic %reg1, #42nt"
 	: /* outputs */ : /* inputs */ : /* clobbers */);
 ```
 
-GCC extensions
---------------
-
-GCC is the only officially-supported compiler for coreboot, and a
-variety of its C language extensions are heavily used throughout the
-code base. There have been occasional attempts to add clang as a second
-compiler option, which is generally compatible to the same language
-extensions that have been long-established by GCC.
-
-Some GCC extensions (e.g. inline assembly) are basically required for
-proper firmware development. Others enable more safe or flexible
-coding patterns than can be expressed with standard C (e.g. statement
-expressions and `typeof()` to avoid double evaluation in macros like
-`MAX()`). Yet others just add some simple convenience and reduce
-boilerplate (e.g. `void *` arithmetic).
-
-Since some GCC extensions are necessary either way, there is no gain
-from avoiding other GCC extensions elsewhere. The use of all official
-GCC extensions is expressly allowed within coreboot. In cases where an
-extension can be replaced by a 100% equivalent C standard feature with
-no extra boilerplate or loss of readability, the C standard feature
-should be preferred (this usually only happens when GCC retains an
-older pre-standardization extension for backwards compatibility, e.g.
-the old pre-C99 syntax for designated initializers). But if there is
-any advantage offered by the GCC extension (e.g. using GCC zero-length
-arrays instead of C99 variable-length arrays because they don't inhibit
-`sizeof()`), there is no reason to deprive ourselves of that, and "this
-is not C standard compliant" should not be a reason to argue against
-its use in reviews.
-
-This rule only applies to explicit GCC extensions listed in the
-"Extensions to the C Language Family" section of the GCC manual. Code
-should never rely on incidental GCC translation behavior that is not
-explicitly documented as a feature and could change at any moment.
-
 References
 ----------
 
 The C Programming Language, Second Edition by Brian W. Kernighan and
 Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
 (paperback), 0-13-110370-9 (hardback). URL:
-<https://duckduckgo.com/?q=isbn+0-13-110362-8> or
-<https://www.google.com/search?q=isbn+0-13-110362-8.
-
+<http://cm.bell-labs.com/cm/cs/cbook/>
 
 The Practice of Programming by Brian W. Kernighan and Rob Pike.
 Addison-Wesley, Inc., 1999. ISBN 0-201-61586-X. URL:
-<https://duckduckgo.com/?q=ISBN+0-201-61586-X> or
-<https://www.google.com/search?q=ISBN+0-201-61586-X>
+<http://cm.bell-labs.com/cm/cs/tpop/>
 
 GNU manuals - where in compliance with K&R and this text - for cpp, gcc,
 gcc internals and indent, all available from

Documentation/contributing/gsoc.md

@@ -1,275 +0,0 @@
-# Google Summer of Code
-
-
-## Contacts
-
-If you are interested in participating in GSoC as a contributor or mentor,
-please have a look at our [community forums] and reach out to us. Working closely
-with the community is highly encouraged, as we've seen that our most successful
-contributors are generally very involved.
-
-Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
-2022. Please feel free to reach out to them directly if you have any questions.
-
-
-## Why work on coreboot for GSoC?
-
-  * coreboot offers you the opportunity to work with various architectures
-    right on the iron. coreboot supports both current and older silicon for a
-    wide variety of chips and technologies.
-
-  * coreboot has a worldwide developer and user base.
-
-  * We are a very passionate team, so you will interact directly with the
-    project initiators and project leaders.
-
-  * We have a large, helpful community. coreboot has some extremely talented
-    and helpful experts in firmware involved in the project. They are ready to
-    assist and mentor contributors participating in GSoC.
-
-  * One of the last areas where open source software is not common is firmware.
-    Running proprietary firmware can have severe effects on user's freedom and
-    security. coreboot has a mission to change that by providing a common
-    framework for initial hardware initialization and you can help us succeed.
-
-
-## Collection of official GSoC guides & documents
-
-  * [Timeline][GSoC Timeline]
-
-  * [Roles and Responsibilities][GSoC Roles and Responsibilities]
-
-  * [Contributor Guide][GSoC Contributor Guide]
-
-  * [Contributor Advice][GSoC Contributor Advice]
-
-  * [Mentor Guide][GSoC Mentor Guide]
-
-  * [FAQ][GSoC FAQ]
-
-  * [Rules][GSoC Rules]
-
-  * [Glossary][GSoC Glossary]
-
-
-## Contributor requirements & commitments
-
-Google Summer of Code is a significant time commitment for you. Medium-sized
-projects are estimated to take 175 hours, while large-sized projects are
-estimated to take 350 hours. Depending on the project size, this means we
-expect you to work roughly half-time or full-time on your project during the
-three months of coding. We expect to be able to see this level of effort in the
-results.
-
-The standard program duration is 12 weeks and in consultation with the mentor
-it can be extended up to 22 weeks. Please keep in mind that the actual number
-of hours you spend on the project highly depends on your skills and previous
-experience.
-
-Make sure that your schedule (exams, courses, day job) gives you a sufficient
-amount of spare time. If this is not the case, then you should not apply.
-
-
-### Before applying
-
-  * Join the [mailing list] and our other [community forums]. Introduce yourself
-    and mention that you are a prospective GSoC contributor. Ask questions and
-    discuss the project that you are considering. Community involvement is a
-    key component of coreboot development.
-
-  * You accept our [Code of Conduct] and [Language style].
-
-  * Demonstrate that you can work with the coreboot codebase.
-
-    * Look over some of the development processes guidelines: [Getting started],
-      [Tutorial], [Flashing firmware tutorial] and [Coding style].
-
-    * Download, build and boot coreboot in QEMU or on real hardware. Please email
-      your serial output results to the [mailing list].
-
-    * Look through some patches on Gerrit to get an understanding of the review
-      process and common issues.
-
-    * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check the [easy project list][Project ideas] or ask for simple tasks on
-      the [mailing list] or on our other [community forums] if you need ideas.
-
-
-### During the program
-
-  * To pass and to be paid by Google requires that you meet certain milestones.
-
-    * First, you must be in good standing with the community before the official
-      start of the program. We expect you to post some design emails to the
-      [mailing list], and get feedback on them, both before applying, and during
-      the "community bonding period" between acceptance and official start.
-
-    * You must have made progress and committed significant code before the
-      mid-term point and by the final.
-
-    * We require that accepted contributors to maintain a blog, where you are
-      expected to write about your project *WEEKLY*. This is a way to measure
-      progress and for the community at large to be able to help you. GSoC is
-      *NOT* a private contract between your mentor and you.
-
-  * You must be active in the community on IRC and the [mailing list].
-
-  * You are expected to work on development publicly, and to push commits to the
-    project on a regular basis. Depending on the project and what your mentor
-    agrees to, these can be published directly to the project or to a public
-    repository such as Gitlab or Github. If you are not publishing directly to
-    the project codebase, be aware that we do not want large dumps of code that
-    need to be rushed to meet the mid-term and final goals.
-
-We don't expect our contributors to be experts in our problem domain, but we
-don't want you to fail because some basic misunderstanding was in your way of
-completing the task.
-
-
-## Projects
-
-There are many development tasks available in coreboot. We prepared some ideas
-for Summer of Code projects. These are projects that we think can be managed in
-the timeline of GSoC, and they cover areas where coreboot is trying to reach
-new users and new use cases.
-
-Of course your application does not have to be based on any of the ideas listed.
-It is entirely possible that you have a great idea that we just didn't think of
-yet. Please let us know!
-
-The blog posts related to previous GSoC projects might give some insights to
-what it is like to be a coreboot GSoC contributor.
-
-
-## coreboot Summer of Code Application
-
-coreboot welcomes contributors from all backgrounds and levels of experience.
-
-Your application should include a complete project proposal. You should
-document that you have the knowledge and the ability to complete your proposed
-project. This may require a little research and understanding of coreboot prior
-to sending your application. The community and coreboot project mentors are your
-best resource in fleshing out your project ideas and helping with a project
-timeline. We recommend that you get feedback and recommendations on your
-proposal before the application deadline.
-
-Please complete the standard GSoC application and project proposal. Provide the
-following information as part of your application. Make sure to provide multiple
-ways of communicating in case your equipment (such as a laptop) is lost,
-damaged, or stolen, or in case of a natural disaster that disrupts internet
-service. You risk automatically failing if your mentor cannot contact you and if
-you cannot provide updates according to GSoC deadlines.
-
-**Personal Information**
-
-  * Name
-
-  * Email and contact options (IRC, Matrix, …)
-
-  * Phone number (optional, but recommended)
-
-  * Timezone, Usual working hours (UTC)
-
-  * School / University, Degree Program, expected graduation date
-
-  * Short bio / Overview of your background
-
-  * What are your other time commitments? Do you have a job, classes, vacations?
-    When and how long?
-
-**Software experience**
-
-If applicable, please provide the following information:
-
-  * Portfolio, Website, blog, microblog, Github, Gitlab, ...
-
-  * Links to one or more patches submitted
-
-  * Links to posts on the [mailing list] with the serial output of your build.
-
-  * Please comment on your software and firmware experience.
-
-  * Have you contributed to an open source project? Which one? What was your
-    experience?
-
-  * What was your experience while building and running coreboot? Did you have
-    problems?
-
-**Your project**
-
-  * Provide an overview of your project (in your own words).
-
-  * Provide a breakdown of your project in small specific weekly goals. Think
-    about the potential timeline.
-
-  * How will you accomplish this goal? What is your working style?
-
-  * Explain what risks or potential problems your project might experience.
-
-  * What would you expect as a minimum level of success?
-
-  * Do you have a stretch goal?
-
-**Other**
-
-  * Resume (optional)
-
-
-### Advice on how to apply
-
-  * [GSoC Contributor Guide]
-
-  * The Drupal project has a great page on how to write an GSoC application.
-
-  * Secrets for GSoC success: [2]
-
-
-## Mentors
-
-Each accepted project will have at least one mentor. We will match mentors and
-contributors based on the project and experience level. If possible, we also
-will try to match their time zones.
-
-Mentors are expected to stay in frequent contact with the contributor and
-provide guidance such as code reviews, pointers to useful documentation, etc.
-This should generally be a time commitment of several hours per week.
-
-Some projects might have more than one mentor, who can serve as a backup. They
-are expected to coordinate with each other and a contributor on a regular basis,
-and keep track of the contributor process. They should be able to take over
-mentoring duty if one of the mentors is unavailable (vacations, sickness,
-emergencies).
-
-
-### Volunteering to be a mentor
-
-If you'd like to volunteer to be a mentor, please read the [GSoC Mentor Guide].
-This will give you a better idea of expectations, and where to go for help.
-After that, contact Org Admins (see coreboot contacts section above).
-
-The following coreboot developers have volunteered to be GSoC 2022 mentors.
-Please stop by in our community forums and say hi to them and ask them
-questions.
-
-  * Tim Wawrzynczak
-  * Raul Rangel
-  * Ron Minnich
-
-
-[community forums]: ../community/forums.md
-[mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org
-[Getting started]: ../getting_started/index.md
-[Tutorial]: ../tutorial/index.md
-[Flashing firmware tutorial]: ../tutorial/flashing_firmware/index.md
-[Coding style]: coding_style.md
-[Code of Conduct]: ../community/code_of_conduct.md
-[Language style]: ../community/language_style.md
-[Project ideas]: project_ideas.md
-[GSoC Timeline]: https://developers.google.com/open-source/gsoc/timeline
-[GSoC Roles and Responsibilities]: https://developers.google.com/open-source/gsoc/help/responsibilities
-[GSoC Contributor Guide]: https://google.github.io/gsocguides/student
-[GSoC Contributor Advice]: https://developers.google.com/open-source/gsoc/help/student-advice
-[GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor
-[GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
-[GSoC Rules]: https://summerofcode.withgoogle.com/rules
-[GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary

Documentation/contributing/index.md

@@ -1,7 +0,0 @@
-# Contributing
-
-* [Coding Style](coding_style.md)
-* [Gerrit Guidelines](gerrit_guidelines.md)
-* [Project Ideas](project_ideas.md)
-* [Documentation Ideas](documentation_ideas.md)
-* [Google Summer of Code](gsoc.md)

Documentation/contributing/project_ideas.md

@@ -20,24 +20,6 @@ doubt if you can bring yourself up to speed in a required time frame
 with the projects. We can then try together to figure out if you're a
 good match for a project, even when requirements might not all be met.
 
-## Easy projects
-
-This is a collection of tasks which don't require deep knowledge on
-coreboot itself. If you are a beginner and want to get familiar with the
-the project and the code base, or if you just want to get your hands
-dirty with some easy tasks, then these are for you.
-
-  * Resolve static analysis issues reported by [scan-build] and
-    [Coverity scan]. More details on the page for
-    [Coverity scan integration].
-
-  * Resolve issues reported by the [linter][Linter issues]
-
-[scan-build]: https://coreboot.org/scan-build/
-[Coverity scan]: https://scan.coverity.com/projects/coreboot
-[Coverity scan integration]: ../infrastructure/coverity.md
-[Linter issues]: https://qa.coreboot.org/job/untested-coreboot-files/lastSuccessfulBuild/artifact/lint.txt
-
 ## Provide toolchain binaries
 Our crossgcc subproject provides a uniform compiler environment for
 working on coreboot and related projects. Sadly, building it takes hours,

Documentation/distributions.md

@@ -24,13 +24,6 @@ ships with coreboot and support upstream maintenance for the devices through a
 third party, [3mdeb](https://3mdeb.com). They provide current and tested
 firmware binaries on [GitHub](https://pcengines.github.io).
 
-### Star Labs
-
-[Star Labs](https://starlabs.systems/) offers a range of laptops designed and
-built specifically for Linux that are available with coreboot firmware. They
-use Tianocore as the payload and include an NVRAM option to disable the
-Intel Management Engine.
-
 ### System76
 
 [System76](https://system76.com/) manufactures Linux laptops, desktops, and

Documentation/getting_started/gerrit_guidelines.md

@@ -193,10 +193,8 @@ the wip flag:
 * When pushing patches that are not for submission, these should be marked
 as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
 private changes, so that only explicitly added reviewers will see them. These
-sorts of patches are frequently posted as ideas or RFCs for the community to
-look at. Note that private changes can still be fetched from Gerrit by anybody
-who knows their commit ID, so don't use this for sensitive changes. To push
-a private change, use the command:
+sorts of patches are frequently posted as ideas or RFCs for the community
+to look at. To push a private change, use the command:
         git push origin HEAD:refs/for/master%private
 
 * Multiple push options can be combined:

Documentation/getting_started/gpio.md

@@ -162,82 +162,6 @@ The first is configuring a pin as an output, when it was designed to be an
 input. There is a real risk in this case of short-circuiting a component which
 could cause catastrophic failures, up to and including your mainboard!
 
-### Intel SoCs
-
-As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
-supports four different types of GPIO reset as:
-
-```eval_rst
-+------------------------+----------------+-------------+-------------+
-|                        |                |         PAD Reset ?       |
-+ PAD Reset Config       + Platform Reset +-------------+-------------+
-|                        |                |     GPP     |     GPD     |
-+========================+================+=============+=============+
-| | 00 - Power Good      |  Warm Reset    |     N       |    N        |
-| | (GPP: RSMRST,        +----------------+-------------+-------------+
-| | GPD: DSW_PWROK)      |  Cold Reset    |     N       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     N       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     N       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     Y       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     Y       |    Y        |
-+------------------------+----------------+-------------+-------------+
-| 01 - Deep              |  Warm Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Cold Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     N       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     Y       |    Y        |
-+------------------------+----------------+-------------+-------------+
-| 10 - Host Reset/PLTRST |  Warm Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Cold Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     Y       |    Y        |
-+------------------------+----------------+-------------+-------------+
-| | 11 - Resume Reset    |  Warm Reset    |     n/a     |    N        |
-| | (GPP: Reserved,      +----------------+-------------+-------------+
-| | GPD: RSMRST)         |  Cold Reset    |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     n/a     |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     n/a     |    Y        |
-+------------------------+----------------+-------------+-------------+
-```
-
-Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
-specific register fields in the PAD configuration register.
-
-The Pad Config Lock registers reset type is default hardcoded to **Power Good** and
-it's **not** configurable by GPIO PAD DW0.PadRstCfg. Hence, it may appear that for a GPP,
-the Pad Reset Config (DW0 Bit 31) is configured differently from `Power Good`.
-
-This would create confusion where the Pad configuration is returned to its `default`
-value but remains `locked`, this would prevent software to reprogram the GPP.
-Additionally, this means software can't rely on GPIOs being reset by PLTRST# or Sx entry.
-
-Hence, as per GPIO BIOS Writers Guide (BWG) it's recommended to change the Pad Reset
-Configuration for lock GPP as `Power Good` so that pad configuration and lock bit are
-always in sync and can be reset at the same time.
-
 ## Soft Straps
 
 Soft straps, that can be configured by the vendor in the Intel Flash Image Tool

Documentation/getting_started/index.md

@@ -4,5 +4,7 @@
 * [Build System](build_system.md)
 * [Submodules](submodules.md)
 * [Kconfig](kconfig.md)
+* [Gerrit Guidelines](gerrit_guidelines.md)
+* [Documentation License](license.md)
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)

Documentation/getting_started/kconfig.md

@@ -786,7 +786,7 @@ select <symbol> \[if <expr>\]
     config TPM
         bool
         default n
-        select MEMORY_MAPPED_TPM if ARCH_X86
+        select LPC_TPM if ARCH_X86
         select I2C_TPM if ARCH_ARM
         select I2C_TPM if ARCH_ARM64
         help

Documentation/getting_started/writing_documentation.md

@@ -159,5 +159,5 @@ TOC tree.
 [guide]: http://www.sphinx-doc.org/en/stable/install.html
 [Sphinx]: http://www.sphinx-doc.org/en/master/
 [Markdown Guide]: https://www.markdownguide.org/
-[Gerrit Guidelines]: ../contributing/gerrit_guidelines.md
+[Gerrit Guidelines]: gerrit_guidelines.md
 [review.coreboot.org]: https://review.coreboot.org

Documentation/index.md

@@ -168,8 +168,14 @@ Contents:
 
 * [Getting Started](getting_started/index.md)
 * [Tutorial](tutorial/index.md)
-* [Contributing](contributing/index.md)
-* [Community](community/index.md)
+* [Coding Style](contributing/coding_style.md)
+* [Project Ideas](contributing/project_ideas.md)
+* [Documentation Ideas](contributing/documentation_ideas.md)
+* [Code of Conduct](community/code_of_conduct.md)
+* [Language style](community/language_style.md)
+* [Community forums](community/forums.md)
+* [Project services](community/services.md)
+* [coreboot at conferences](community/conferences.md)
 * [Payloads](payloads.md)
 * [Distributions](distributions.md)
 * [Technotes](technotes/index.md)
@@ -188,6 +194,6 @@ Contents:
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
-* [Project infrastructure & services](infrastructure/index.md)
-* [Release notes](releases/index.md)
-* [Documentation License](documentation_license.md)
+* [coreboot infrastructure](infrastructure/index.md)
+* [Release notes for past releases](releases/index.md)
+* [Flashing firmware tutorial](flash_tutorial/index.md)

Documentation/infrastructure/builders.md

@@ -8,8 +8,8 @@ Let a jenkins admin know that you’re interested in setting up a jenkins
 build system.
 
 For a permanent build system, this should generally be a dedicated
-machine workstation or server class machine that is not generally being
-used for other purposes.  The coreboot builds are very intensive.
+machine that is not generally being used for other purposes.  The
+coreboot builds are very intensive.
 
 It's also best to be aware that although we don't know of any security
 issues, the jenkins-node image is run with the privileged flag which
@@ -26,40 +26,34 @@ Currently active Jenkins admins:
 *   Patrick Georgi:
     *   Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de)
     *   IRC: pgeorgi
-*   Martin Roth:
-    *   Email: [gaumless@gmail.com](mailto:gaumless@gmail.com)
-    *   IRC: martinr
+
 
 ### Build Machine requirements
 
-For a builder, we need a very fast system with lots of threads and
-plenty of RAM.  The builder builds and stores the git repos and output
-in tmpfs along with the ccache save area, so if there isn't enough
-memory, the builds will slow down because of smaller ccache areas and
-can run into "out of storage space" errors.
+For a builder, we need a fast system with lots of threads and plenty of
+RAM.  The builder builds and stores the git repos and output in tmpfs
+along with the ccache save area, so if there isn't enough memory, the
+builds will slow down because of smaller ccache areas and can run into
+"out of storage space" errors.
 
 #### Current Build Machines
 
 To give an idea of what a suitable build machine might be, currently the
-coreboot project has 4 active jenkins build machines.
-
-These times are taken from the week of Feb 21 - Feb 28, 2022
+coreboot project has 3 active jenkins build machines.
 
 * Congenialbuilder - 128 threads, 256GiB RAM
-  *  Fastest Passing coreboot gerrit build: 6 min, 47 sec
-  *  Slowest Passing coreboot gerrit build: 14 min
+  *  Fastest Passing coreboot gerrit build: 4 min, 30 sec
+  *  Slowest Passing coreboot gerrit build: 9 min, 56 sec
 
-* Gleefulbuilder - 64 thread, 64GiB RAM
-  *  Fastest Passing coreboot gerrit build: 10 min
-  *  Slowest Passing coreboot gerrit build: 46 min
 
-* Fabulousbuilder - 64 threads, 64GiB RAM
-  *  Fastest Passing coreboot gerrit build: 7 min, 56 sec
-  *  Slowest Passing coreboot gerrit build: 56 min (No ccache)
+* Gleeful builder - 64 thread, 64GiB RAM
+  *  Fastest Passing coreboot gerrit build: 6 min, 6 sec
+  *  Slowest Passing coreboot gerrit build, 34 min
+
 
 * Ultron (9elements) - 48 threads, 128GiB RAM
-  *  Fastest Passing coreboot gerrit build: 12
-  *  Slowest Passing coreboot gerrit build: 58 min
+  *  Fastest Passing coreboot gerrit build: 6 min, 32 sec
+  *  Slowest Passing coreboot gerrit build: 44 min
 
 
 ### Jenkins Builds
@@ -67,13 +61,13 @@ These times are taken from the week of Feb 21 - Feb 28, 2022
 There are a number of builds handled by the coreboot jenkins builders,
 for a number of different projects - coreboot, flashrom, memtest86+,
 em100, etc.  Many of these have builders for their current master branch
-as well as Gerrit and [Coverity](coverity.md) builds.
+as well as gerrit and coverity builds.
 
 You can see all the builds here:
 [https://qa.coreboot.org/](https://qa.coreboot.org/)
 
 Most of the time on the builders is taken up by the coreboot master and
-coreboot gerrit builds.
+gerrit builds.
 
 * [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
 ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
@@ -133,23 +127,10 @@ the machine remotely (if you allow them).
 
 ### Install and set up docker
 
-Install docker by following [the
-directions](https://docs.docker.com/engine/install/) on the docker site.
-These instructions keep changing, so just check the latest information.
-
-
-### Set up the system for the jenkins builder
-
-As a regular user - *Not root*, run:
-
-```
-sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
-sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
-sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
-sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR}
-wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar
-mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR}
-```
+Install docker by following the
+[directions](https://docs.docker.com/engine/install/) on the docker
+site.  These instructions keep changing, so just check the latest
+information.
 
 
 #### Set up environment variables
@@ -162,8 +143,8 @@ using something other than the default.
 # Set the port used on your machine to connect to jenkins.
 export COREBOOT_JENKINS_PORT=49151
 
-# Set the revision of the container from [docker hub](https://hub.docker.com/repository/docker/coreboot/coreboot-sdk)
-export DOCKER_COMMIT=2021-09-23_b0d87f753c
+# Set the revision of the container from docker hub
+export DOCKER_COMMIT=65718760fa
 
 # Set the location of where the jenkins cache directory will be.
 export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache"
@@ -218,6 +199,18 @@ Variables:
   DOCKER_COMMIT=65718760fa
 ```
 
+### Set up the system for the jenkins builder
+
+As a regular user - *Not root*, run:
+
+```
+sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
+sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
+sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
+sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR}
+wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar
+mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR}
+```
 
 ### Install the coreboot jenkins builder
 
@@ -233,17 +226,17 @@ machine profile on qa.coreboot.org.
 
 They need to know:
 *   Your external IP address or domain name.  If you don’t have a static
-    IP, make sure you have a dynamic dns hostname configured.
+IP, make sure you have a dynamic dns hostname configured.
 *   The port on your machine and firewall that’s exposed for jenkins:
-    `$COREBOOT_JENKINS_PORT`
+`$COREBOOT_JENKINS_PORT`
 *   The core count of the machine.
 *   How much memory is available on the machine.  This helps determine
-    the amount of memory used for ccache.
+the amount of memory used for ccache.
 
 
 ### First build
 On the first build after a machine is reset, it will frequently take
-an hour to do the entire what-jenkins-does build while the ccache
+20-25 minutes to do the entire what-jenkins-does build while the ccache
 is getting filled up and the entire coreboot repo gets downloaded.  As
 the ccache gets populated, the build time will drop.
 
@@ -261,12 +254,12 @@ the ccache gets populated, the build time will drop.
 
 
 WARNING: This should not be used to make changes to the build system,
-but just to debug issues. Changes to the build system image are highly
+but just to debug issues. Changes to the build system are highly
 discouraged as it leads to situations where patches can pass the build
 testing on one builder and fail on another builder. Any changes that are
 made in the image will be lost on the next update, so if you
-accidentally change something, you can remove the containers and images,
-then update to get a fresh installation.
+accidentally change something, you can remove the containers and images
+and update to get a fresh installation.
 
 
 ### How to download containers/images for a fresh installation and remove old containers
@@ -383,7 +376,6 @@ to be marked as a coverity builder.
 
 Download the Linux-64 coverity build tool and decompress it into your
 cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable
-on the jenkins server.
 
 [https://scan.coverity.com/download](https://scan.coverity.com/download)
 

Documentation/infrastructure/coverity.md

@@ -1,103 +0,0 @@
-# Coverity Scan for open source firmware
-
-## What’s Coverity and Coverity Scan?
-
-Coverity is a static analysis tool. It hooks into the build process
-and in addition to the compiler creating object files, Coverity collects
-information about the code. That data is then processed in a separate pass
-to identify common programming errors, like out of bounds accesses in C.
-
-Coverity Scan is an online service for Open Source projects providing this
-analysis for free. The analysis pass is done on their servers and issues
-can be handled in their [web UI](https://scan.coverity.com/).
-
-The Scan service has some quotas based on code size to avoid overloading
-the system, but even at one build per week, that’s usually good enough
-because the identified issues still need to be triaged and fixed or they
-will simply be re-identified next week.
-
-### Triage?
-
-The Web UI looks a bit like an issue tracker, even if it’s not a very
-good one. It’s possible to mark identified issues as valid or invalid,
-and annotate them with metadata which CLs fix them. The latter isn’t
-strictly necessary because Coverity Scan simply marks issues it can’t
-find anymore as fixed, but at times it helped identify issues that made
-a comeback.
-
-### Alternatives
-
-There’s also clang’s scan-build, which is fully open-source, and
-finds different issues. As such, it’s less of an alternative and more
-of a complement.
-
-There’s a regular run of that for coreboot but not for the other projects
-hosted at coreboot.org.
-
-One downside is that it emits a bunch of HTML to report on issues,
-but there’s no interactivity (e.g. marking issues solved), no way
-to merge multiple builds (e.g. multiple board builds of a single tree)
-or a simple way to extract burndown charts and the like from that.
-
-#### Looking for a project?
-
-On the upside, it can emit the data in a machine readable format, so if
-anybody needs a project, a scan-build web-frontend like Coverity Scan would
-be feasible without having to go through scan-build’s guts, just by parsing
-text files - plus all the stateful and web parts to build on top.
-
-## Logging into Coverity Scan
-
-Coverity Scan needs an account. It supports its own accounts and GitHub
-OAuth.
-
-Access to the dashboards needs approval: Request and you shall receive.
-
-## coreboot & friends and Coverity Scan
-
-coreboot, flashrom, Chromium EC and other projects of that family have
-been made Coverity aware, that is, their build systems support building
-with a custom compiler configuration passed in “just right” to enable
-Coverity to add its hooks.
-
-The public coreboot CI system at
-[https://qa.coreboot.org/](https://qa.coreboot.org/) regularly does
-builds with Coverity and sends them off to Coverity Scan.
-
-Specifically, it covers:
-
-* Chromium EC: [Coverity Scan site][crECCoverity] ([build job][crECBuildJob])
-* coreboot: [Coverity Scan site][corebootCoverity] ([build job][corebootBuildJob]), [scan-build output][corebootScanBuild] ([build job][corebootScanBuildJob])
-* em100: [Coverity Scan site][em100Coverity] ([build job][em100BuildJob])
-* fcode-utils: [Coverity Scan site][fcodeUtilsCoverity] ([build job][fcodeUtilsBuildJob])
-* flashrom: [Coverity Scan site][flashromCoverity] ([build job][flashromBuildJob])
-* memtest86+: [Coverity Scan site][memtestCoverity] ([build job][memtestBuildJob])
-* vboot: [Coverity Scan site][vbootCoverity] ([build job][vbootBuildJob])
-
-[crECCoverity]: https://scan.coverity.com/projects/chromium-ec
-[corebootCoverity]: https://scan.coverity.com/projects/coreboot
-[em100Coverity]: https://scan.coverity.com/projects/em100
-[fcodeUtilsCoverity]: https://scan.coverity.com/projects/fcode-utils
-[flashromCoverity]: https://scan.coverity.com/projects/flashrom
-[memtestCoverity]: https://scan.coverity.com/projects/memtest86
-[vbootCoverity]: https://scan.coverity.com/projects/vboot
-
-[corebootScanBuild]: https://www.coreboot.org/scan-build/
-
-[crECBuildJob]: https://qa.coreboot.org/view/coverity/job/ChromeEC-Coverity/
-[corebootBuildJob]: https://qa.coreboot.org/view/coverity/job/coreboot-coverity/
-[corebootScanBuildJob]: https://qa.coreboot.org/view/coverity/job/coreboot_scanbuild/
-[em100BuildJob]: https://qa.coreboot.org/view/coverity/job/em100-coverity/
-[fcodeUtilsBuildJob]: https://qa.coreboot.org/view/coverity/job/fcode-utils-coverity/
-[flashromBuildJob]: https://qa.coreboot.org/view/coverity/job/flashrom-coverity/
-[memtestBuildJob]: https://qa.coreboot.org/view/coverity/job/memtest86plus-coverity/
-[vbootBuildJob]: https://qa.coreboot.org/view/coverity/job/vboot-coverity/
-
-Some projects (e.g. Chromium EC) build a different subset of boards on
-each run, ensuring that everything is analyzed eventually. The downside
-is that coverity issues pop up and disappear somewhat randomly as they
-are discovered and go unnoticed in a later build.
-
-More projects that are hosted on review.coreboot.org (potentially as a
-mirror, like vboot and EC) could be served through that pipeline. Reach
-out to {stepan,patrick,martin}@coreboot.org.

Documentation/infrastructure/index.md

@@ -1,12 +1,6 @@
-# Project infrastructure & services
-
-This section contains documentation about our infrastructure
-
-## Services
-
-* [Project services](services.md)
+# coreboot infrastructure
 
+This section contains documentation about coreboot infrastructure
 
 ## Jenkins builders and builds
 * [Setting up Jenkins build machines](builders.md)
-* [Coverity Scan integration](coverity.md)

Documentation/mainboard/acer/g43t-am3.md

@@ -1,177 +0,0 @@
-# Acer G43T-AM3
-
-The Acer G43T-AM3 is a microATX-sized desktop board. It was used for the
-Acer models Aspire M3800, Aspire M5800 and possibly more.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel G43 (called x4x in coreboot code)          |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel ICH10R (called i82801jx in coreboot code)  |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 775                                          |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1066                                    |
-+------------------+--------------------------------------------------+
-| SuperIO          | ITE IT8720F                                      |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC888S                                  |
-+------------------+--------------------------------------------------+
-| Network          | Intel 82567V-2 Gigabit Ethernet                  |
-+------------------+--------------------------------------------------+
-```
-
-There is no serial port. Serial console output is possible by soldering
-to a point at the corresponding Super I/O pin and patching the
-mainboard-specific code accordingly.
-
-## Status
-
-### Working
-
-Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
-(linux-4.19.50).
-
-+ Intel Core 2 processors at up to FSB 1333
-+ All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
-+ Integrated graphics (libgfxinit)
-+ HDMI and VGA ports
-+ Both PCI slots
-+ Both PCI-e slots
-+ USB (8 internal, 4 external)
-+ All six SATA ports
-+ Onboard Ethernet
-+ Onboard sound card with output on the rear stereo connector
-+ PS/2 mouse and keyboard
-    + With SeaBIOS, use CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500
-    + With FILO it works without further settings
-+ Temperature readings from the Super I/O (including the CPU temperature
-  via PECI)
-+ Super I/O EC automatic fan control
-+ S3 suspend/resume
-+ Poweroff
-
-### Not working
-
-+ DDR3 memory with 512Mx8 chips (G43 limitation)
-+ 4x4GB of DDR3 memory (works, but showed a single bit error within one
-  pass of Memtest86+ 5.01)
-+ Super I/O voltage reading conversions
-
-### Untested
-
-+ Other audio jacks or the front panel header
-+ S/PDIF output
-+ On-board Firewire
-+ Wake-on-LAN
-
-## Flashing coreboot
-
-```eval_rst
-+-------------------+---------------------+
-| Type              | Value               |
-+===================+=====================+
-| Socketed flash    | No                  |
-+-------------------+---------------------+
-| Model             | Macronix MX25L1605D |
-+-------------------+---------------------+
-| Size              | 2 MiB               |
-+-------------------+---------------------+
-| Package           | 8-Pin SOP           |
-+-------------------+---------------------+
-| Write protection  | No                  |
-+-------------------+---------------------+
-| Dual BIOS feature | No                  |
-+-------------------+---------------------+
-| Internal flashing | Yes                 |
-+-------------------+---------------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-```
-00000000:00001fff fd
-00100000:001fffff bios
-00006000:000fffff me
-00002000:00005fff gbe
-```
-
-In general, flashing is possible internally and from an external header. It
-might be necessary to specify the chip type; `MX25L1605D/MX25L1608D/MX25L1673E`
-is the correct one, not `MX25L1605`.
-
-### Internal flashing
-
-Internal access to the flash chip is unrestricted. When installing coreboot,
-only the BIOS region should be updated by passing the `--ifd` and `-i bios`
-parameters to flashrom. A full backup is advisable.
-
-Here is an example:
-
-```
-$ sudo flashrom \
-  -p internal \
-  -c "MX25L1605D/MX25L1608D/MX25L1673E" \
-  -r backup.rom
-$ sudo flashrom \
-  -p internal \
-  -c "MX25L1605D/MX25L1608D/MX25L1673E" \
-  --ifd -i bios \
-  -w coreboot.rom
-```
-
-```eval_rst
-In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
-
-### External flashing
-
-The SPI flash chip on this board can be flashed externally through the
-SPI_ROM1 header while the board is off and disconnected from power. There
-seems to be a diode that prevents the external programmer from powering the
-whole board.
-
-The signal assigment on the header is identical to the pinout of the flash
-chip. The pinout diagram below is valid when the PCI slots are on the left
-and the CPU is on the right. Note that HOLD# and WP# must be pulled high
-(to VCC) to be able to flash the chip.
-
-                +---+---+
-     SPI_CSn <- | x | x | -> VCC
-                +---+---+
-    SPI_MISO <- | x | x | -> HOLDn
-                +---+---+
-         WPn <- | x | x | -> SPI_CLK
-                +---+---+
-         GND <- | x | x | -> SPI_MOSI
-                +---+---+
-
-## Intel Management Engine
-
-The Intel Management Engine (ME) can be disabled by setting the ME_DISABLE
-jumper on the board. It pulls GPIO33 on the ICH10 low, causing the "Flash
-Descriptor Security Override Strap" to be set. This disables the ME and also
-disables any read/write restrictions to the flash chip that may be set in the
-Intel Flash Descriptor (IFD) (none on this board). Note that changing this
-jumper only comes into effect when starting the board from a shutdown or
-suspend state, not during normal operation.
-
-To completely remove the ME blob from the flash image and to decrease the size
-of the ME region, thus increasing the size of the BIOS region, `me_cleaner` can
-be used with the `-t`, `-r` and `-S` options.
-
-## Fan control
-
-There are two fan connectors that can be controlled individually. CPU_FAN
-can only control a fan by a PWM signal and SYS_FAN only by voltage. See
-the mainboard's `devicetree.cb` file for how coreboot configures the Super
-I/O to control the fans.
-
-## Variants
-
-Various similar mainboards exist, like the Acer Q45T-AM. During a discussion
-in #coreboot on IRC, ECS was suspected to be the original designer of this
-series of mainboards. They have similar models such as the ECS G43T-WM.

Documentation/mainboard/asrock/h110m-dvs.md

@@ -58,7 +58,7 @@ The main SPI flash can be accessed using [flashrom]. By default, only
 the BIOS region of the flash is writable. If you wish to change any
 other region, such as the Management Engine or firmware descriptor, then
 an external programmer is required (unless you find a clever way around
-the flash protection). More information about this [here](../../tutorial/flashing_firmware/index.md).
+the flash protection). More information about this [here](../../flash_tutorial/index.md).
 
 ### External programming
 
@@ -131,4 +131,4 @@ facing towards the bottom of the board.
 [ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
 [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2064Mb,%20v1.4.pdf
 [flashrom]: https://flashrom.org/Flashrom
-[H110M-DVS manual]: https://web.archive.org/web/20191023230631/http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf
+[H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf

Documentation/mainboard/asrock/h77pro4-m.md

@@ -1,174 +0,0 @@
-# ASRock H77 Pro4-M
-
-The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy
-Bridge and Ivy Bridge CPUs.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel H77 (bd82x6x)                              |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 1155                                         |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1600                                    |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton NCT6776                                  |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC892                                   |
-+------------------+--------------------------------------------------+
-| Network          | Realtek RTL8111E                                 |
-+------------------+--------------------------------------------------+
-| Serial           | Internal header (RS-232)                         |
-+------------------+--------------------------------------------------+
-```
-
-## Status
-
-Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
-(linux-4.19.50).
-
-### Working
-
-- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
-- Native RAM initialization with four DIMMs
-- PS/2 combined port (mouse or keyboard)
-- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
-- PCIe graphics in the PEG slot
-- All three additional PCIe slots
-- All rear and internal USB2 ports
-- All rear and internal USB3 ports
-- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
-- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
-- Rear eSATA connector (multiplexed with one ASM1061 port)
-- Gigabit Ethernet
-- Console output on the serial port
-- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via
-extlinux
-- Internal flashing with flashrom-1.2, see
-[Internal Programming](#internal-programming)
-- External flashing with flashrom-1.2 and a Raspberry Pi 1
-- S3 suspend/resume from either Linux or Windows 10
-- Poweroff
-
-### Not working
-
-- Booting from the two SATA ports provided by the ASM1061
-- Automatic fan control with the NCT6776D Super I/O
-
-### Untested
-
-- EHCI debug
-- S/PDIF audio
-- Other audio jacks than the green one, and the front panel header
-- Parallel port
-- Infrared/CIR
-- Wakeup from anything but the power button
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | yes        |
-+---------------------+------------+
-| Model               | W25Q64.V   |
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | DIP-8      |
-+---------------------+------------+
-| Write protection    | no         |
-+---------------------+------------+
-| Dual BIOS feature   | no         |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-```
-00000000:00000fff fd
-00200000:007fffff bios
-00001000:001fffff me
-```
-
-### Internal programming
-
-The main SPI flash can be accessed using flashrom. By default, only
-the BIOS region of the flash is writable. If you wish to change any
-other region (Management Engine or flash descriptor), then an external
-programmer is required.
-
-The following command may be used to flash coreboot:
-
-```
-$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
-```
-
-The use of `--noverify-all` is required since the Management Engine
-region is not readable even by the host.
-
-```eval_rst
-In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
-
-## Hardware monitoring and fan control
-
-There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share
-a single fan tachometer input on the Super I/O while some dedicated logic
-selects which one is allowed to reach it. Two GPIO pins on the Super I/O are
-used to control that logic. The firmware has to set them; coreboot selects
-CPU_FAN1 by default, but the user can change that setting if it was built with
-CONFIG_USE_OPTION_TABLE:
-
-```
-$ sudo nvramtool -e cpu_fan_header
-[..]
-$ sudo nvramtool -w cpu_fan_header=CPU_FAN2
-$ sudo nvramtool -w cpu_fan_header=None
-$ sudo nvramtool -w cpu_fan_header=Both
-```
-
-The setting will take effect after a reboot. Selecting and connecting both fan
-headers is possible but the Super I/O will report wrong fan speeds.
-
-Currently there is no automatic, OS-independent fan control, but a software
-like `fancontrol` from the lm-sensors package can be used instead.
-
-## Serial port header
-
-Serial port 1, provided by the Super I/O, is exposed on a pin header. The
-RS-232 signals are assigned to the header so that its pin numbers map directly
-to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
-work, check if your bracket expects a different assignment. Also don't try to
-connect it directly to a device that operates at TTL levels - it would need a
-level converter like a MAX232.
-
-Here is a top view of the serial port header found on this board:
-
-                 +---+---+
-             N/C |   | 9 | RI  -> pin 9
-                 +---+---+
-    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
-                 +---+---+
-    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
-                 +---+---+
-    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
-                 +---+---+
-    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
-                 +---+---+
-
-## eSATA
-
-The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share
-the same controller port on the ASM1061. Attaching an eSATA drive causes a
-multiplexer chip to disconnect the internal port from the SATA controller and
-connect the eSATA port instead. This can be seen on GP23 of the Super I/O
-GPIOs: it is '0' when something is connected to the eSATA port and '1'
-otherwise.

Documentation/mainboard/asrock/h81m-hds.md

@@ -130,4 +130,4 @@ Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
 [ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/
 [W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
 [flashrom]: https://flashrom.org/Flashrom
-[Board manual]: https://web.archive.org/web/20191231093418/http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf
+[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf

Documentation/mainboard/asus/f2a85-m.md

@@ -190,9 +190,9 @@ This version is usable for all the GPUs.
 - [Board manual]
 - Flash chip datasheet [W25Q64FV]
 
-[ASUS F2A85-M]: https://web.archive.org/web/20160320065008/http://www.asus.com/Motherboards/F2A85M/
-[Board manual]: https://web.archive.org/web/20211028063105/https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf
+[ASUS F2A85-M]: https://www.asus.com/Motherboards/F2A85M/
+[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf
 [flashrom]: https://flashrom.org/Flashrom
 [Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
 [TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
-[W25Q64FV]: https://web.archive.org/web/20220127184640/https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf

Documentation/mainboard/asus/p5q.md

@@ -130,5 +130,5 @@ You can also control the CPU fan with similar rules:
     echo 2000 >/sys/class/hwmon/hwmon2/pwm1_tolerance
 
 [ASUS P5Q]: https://www.asus.com/Motherboards/P5Q
-[this guide]: ../../tutorial/flashing_firmware/int_flashrom.md
+[this guide]: https://doc.coreboot.org/flash_tutorial/int_flashrom.html
 [kernel docs]: https://www.kernel.org/doc/Documentation/hwmon/w83627ehf.rst

Documentation/mainboard/asus/p8h61-m_lx.md

@@ -106,6 +106,6 @@ region is not readable even by the host.
 - [Flash chip datasheet][W25Q32BV]
 
 [ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/
-[W25Q32BV]: https://web.archive.org/web/20211002141814/https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
+[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
 [flashrom]: https://flashrom.org/Flashrom
 [Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip

Documentation/mainboard/emulation/qemu-power9.md

@@ -1,52 +0,0 @@
-# QEMU PPC64 emulator
-This page describes how to build and run coreboot for QEMU/PPC64.
-
-## Building coreboot
-```bash
-make defconfig KBUILD_DEFCONFIG=configs/config.emulation_qemu_power9
-make
-```
-
-This builds coreboot with no payload.
-
-## Payloads
-You can configure ELF or `skiboot` payload via `make menuconfig`. In either case
-you might need to adjust "ROM chip size" and make it large enough to accommodate
-the payload (see how much space it needs in the error you get if it doesn't
-fit).
-
-## Running coreboot in QEMU
-```bash
-qemu-system-ppc64 -M powernv,hb-mode=on \
-                  -cpu power9 \
-                  -bios build/coreboot.rom \
-                  -drive file=build/coreboot.rom,if=mtd \
-                  -serial stdio \
-                  -display none
-```
-
-- The default CPU in QEMU for AArch64 is a 604. You specify a suitable
-PowerPC CPU via `-cpu power9`.
-- By default Hostboot mode is off and needs to be turned on to run coreboot
-as a firmware rather than like an OS.
-- `-bios` specifies initial program (bootloader should suffice, but whole image
-works fine too).
-- `-drive` specifies image for emulated flash device.
-
-## Running with a kernel
-Loading `skiboot` (built automatically by coreboot or otherwise) allows
-specifying kernel and root file system to be run.
-
-```bash
-qemu-system-ppc64 -M powernv,hb-mode=on \
-                  -cpu power9 \
-                  -bios build/coreboot.rom \
-                  -drive file=build/coreboot.rom,if=mtd \
-                  -serial stdio \
-                  -display none \
-                  -kernel zImage \
-                  -initrd initrd.cpio.xz
-```
-
-- Specify path to your kernel via `-kernel`.
-- Specify path to your rootfs via `-initrd`.

Documentation/mainboard/emulation/qemu-riscv.md

@@ -1,8 +1,8 @@
-# QEMU RISC-V emulator
+# Qemu RISC-V emulator
 
-## Building coreboot and running it in QEMU
+## Building coreboot and running it in Qemu
 
 - Configure coreboot and run `make` as usual
 - Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
-  convert coreboot to an ELF that QEMU can load
+  convert coreboot to an ELF that Qemu can load
 - Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf`

Documentation/mainboard/facebook/fbg1701.md

@@ -5,7 +5,10 @@ This page describes how to run coreboot on the Facebook FBG1701.
 FBG1701 are assembled with different onboard memory modules:
 	Rev 1.0	Onboard Samsung K4B8G1646D-MYKO memory
 	Rev 1.1 and 1.2	Onboard Micron MT41K512M16HA-125A memory
-	Rev 1.3 and 1.4 Onboard Kingston B5116ECMDXGGB memory
+	Rev 1.3	Onboard Kingston B5116ECMDXGGB memory
+
+Use make menuconfig to configure `onboard memory manufacturer Samsung` in
+Mainboard menu.
 
 ## Required blobs
 

Documentation/mainboard/gigabyte/ga-g41m-es2l.md

@@ -142,7 +142,7 @@ Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
 
 ```eval_rst
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
+:doc:`../../flash_tutorial/index`.
 ```
 
 ### Do backup

Documentation/mainboard/hp/2560p.md

@@ -94,6 +94,6 @@ Schematic of this laptop can be found on [Lab One].
 
 [HP EliteBook 2560p]: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201
 [Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03011618
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [Lab One]: https://www.laboneinside.com/hp-elitebook-2560p-schematic-diagram/
 [bug #141]: https://ticket.coreboot.org/issues/141

Documentation/mainboard/index.md

@@ -6,16 +6,11 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [X210](51nb/x210.md)
 
-## Acer
-
-- [G43T-AM3](acer/g43t-am3.md)
-
 ## AMD
 - [padmelon](amd/padmelon/padmelon.md)
 
 ## ASRock
 
-- [H77 Pro4-M](asrock/h77pro4-m.md)
 - [H81M-HDS](asrock/h81m-hds.md)
 - [H110M-DVS](asrock/h110m-dvs.md)
 
@@ -48,11 +43,10 @@ This section contains documentation about coreboot on specific mainboards.
 The boards in this section are not real mainboards, but emulators.
 
 - [Spike RISC-V emulator](emulation/spike-riscv.md)
-- [QEMU RISC-V emulator](emulation/qemu-riscv.md)
-- [QEMU AArch64 emulator](emulation/qemu-aarch64.md)
-- [QEMU x86 Q35](emulation/qemu-q35.md)
-- [QEMU x86 PC](emulation/qemu-i440fx.md)
-- [QEMU POWER9](emulation/qemu-power9.md)
+- [Qemu RISC-V emulator](emulation/qemu-riscv.md)
+- [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
+- [Qemu x86 Q35](emulation/qemu-q35.md)
+- [Qemu x86 PC](emulation/qemu-i440fx.md)
 
 ## Facebook
 
@@ -178,16 +172,8 @@ The boards in this section are not real mainboards, but emulators.
 
 - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
 
-## Star Labs Systems
-
-- [LabTop Mk IV](starlabs/labtop_cml.md)
-- [StarLite Mk III](starlabs/lite_glk.md)
-- [StarLite Mk IV](starlabs/lite_glkr.md)
-- [StarBook Mk V](starlabs/starbook_tgl.md)
-
 ## Supermicro
 
-- [X9SAE](supermicro/x9sae.md)
 - [X10SLM+-F](supermicro/x10slm-f.md)
 - [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
 - [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -38,7 +38,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
 * ROM chip size should be set to 12MiB.
 
 ```eval_rst
-Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
+Please also have a look at :doc:`../../flash_tutorial/index`.
 ```
 
 ## Splitting the coreboot.rom
@@ -90,4 +90,4 @@ Tests on Lenovo W530 showed no issues with a stripped and shrunken ME firmware.
 
 
 [me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
-[external programmer]: ../../tutorial/flashing_firmware/index.md
+[external programmer]: ../../flash_tutorial/index.md

Documentation/mainboard/lenovo/Sandy_Bridge_series.md

@@ -70,5 +70,5 @@ the remaining space for the `bios` partition.
 
 
 [me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
-[external programmer]: ../../tutorial/flashing_firmware/index.md
-[flashing tutorial]: ../../tutorial/flashing_firmware/index.md
+[external programmer]: ../../flash_tutorial/index.md
+[flashing tutorial]: ../../flash_tutorial/index.md

Documentation/mainboard/lenovo/ivb_internal_flashing.md

@@ -353,12 +353,9 @@ Verify that it worked:
 
 Bingo!
 
-Now you can [flash internally]. Remember to flash only the `bios` region
-(use `--ifd -i bios -N` flashrom arguments). `fd` and `me` are still
-locked.
+Now you can [flash internally](/flash_tutorial/int_flashrom.md).
+Remember to flash only the `bios` region (use `--ifd -i bios -N`
+flashrom arguments). `fd` and `me` are still locked.
 
 Note that you should have an external SPI programmer as a backup method.
 It will help you recover if you flash non-working ROM by mistake.
-
-
-[flash internally]: ../../tutorial/flashing_firmware/int_flashrom.md

Documentation/mainboard/lenovo/t410.md

@@ -37,7 +37,7 @@ The chip will either be a Macronix MX25L6405D or a Winbond W25Q64CVSIG.
 Do not rely on dots painted in the corner of the chip (such as the blue dot
 pictured) to orient the pins!
 
-[Flashing tutorial](../../tutorial/flashing_firmware/no_ext_power.md)
+[Flashing tutorial](../../flash_tutorial/no_ext_power.md)
 
 Steps to access the flash IC are described here [T4xx series].
 

Documentation/mainboard/lenovo/t420.md

@@ -53,5 +53,5 @@ Steps to access the flash IC are described here [T4xx series].
  * Suspend (Windows 10)
 
 [T4xx series]: t4xx_series.md
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md

Documentation/mainboard/lenovo/t430.md

@@ -9,6 +9,6 @@ the general [flashing tutorial].
 
 Steps to access the flash IC are described here [T4xx series].
 
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T4xx series]: t4xx_series.md
 [T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md

Documentation/mainboard/lenovo/w530.md

@@ -22,5 +22,5 @@ the general [flashing tutorial].
 
 [w530-2]: w530-2.jpg
 
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T430 / T530 / X230 / T430s / W530 common]: Ivy_Bridge_series.md

Documentation/mainboard/lenovo/x1.md

@@ -18,5 +18,5 @@ the general [flashing tutorial].
 Steps to access the flash IC are described here [X2xx series].
 
 [X2xx series]: x2xx_series.md
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md

Documentation/mainboard/lenovo/x230s.md

@@ -16,4 +16,4 @@ is located at the circled place.
 
 Unlike [most Ivy Bridge ThinkPads](Ivy_Bridge_series.md), X230s has a single 16MiB SPI flash chip.
 
-The general [flashing tutorial](../../tutorial/flashing_firmware/index.md) has more details.
+The general [flashing tutorial](../../flash_tutorial/index.md) has more details.

Documentation/mainboard/lenovo/x301.md

@@ -43,5 +43,5 @@ Tested:
   Linux payload (Heads) and SeaBIOS.
 
 
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../flash_tutorial/ext_power.md
 

Documentation/mainboard/msi/ms7707/ms7707.md

@@ -74,7 +74,7 @@ seconds. Setting the jumper alone is not enough (the Fintek is VBAT backed).
 Put all back in place and restart the board. It might need 1-2 AC power cycles
 to reinitialize (running at full fan speed - don't panic).
 * External flashing has been tested with RPi2 without main power connected.
-3.3V provided by RPi2. Read more about [flashing methods].
+3.3V provided by RPi2. Read more about flashing methods [here](https://doc.coreboot.org/flash_tutorial/index.html).
 * In case of going back to proprietary BIOS create/save CMOS settings as early
 as possible (do not leave BIOS on first start without saving settings).
 The BIOS might corrupt nvram (not cmos!) and leave the system in a dead state
@@ -110,4 +110,3 @@ needed (internally re-routed already).
 [Winbond 25Q32BV datasheet]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
 [Fintek F71808A datasheet]: https://www.alldatasheet.com/datasheet-pdf/pdf/459069/FINTEK/F71808A.html
 [flashlayout]: flashlayout.svg
-[flashing methods]: ../../../tutorial/flashing_firmware/index.md

Documentation/mainboard/ocp/deltalake.md

@@ -7,16 +7,7 @@ Delta Lake server platform.
 
 OCP Delta Lake server platform is a component of multi-host server system
 Yosemite-V3. Both [Delta Lake server design spec] and [Yosemite-V3 design
-spec] were [OCP] accepted.
-
-On the other hand, Wiwynn's Yosemite-V3 system and Delta Lake server product
-along with its OSF implementation, which is based on FSP/coreboot/LinuxBoot
-stack, was [OCP] accepted; For details, check:
-- [The OCP blog]
-- [The Wiwynn Press Release]
-- [The Wiwynn's Yosemite-V3 product in OCP market place]
-Wiwynn and 9Elements formed a partnership to offer the Wiwynn's Yosemite-V3
-product and OSF for it.
+spec] were contributed to [OCP].
 
 Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
 Intel Cooper Lake Scalable Processor was launched in Q2 2020.
@@ -24,7 +15,7 @@ Intel Cooper Lake Scalable Processor was launched in Q2 2020.
 Yosemite-V3 has multiple configurations. Depending on configurations, it may
 host up to 4 Delta Lake servers (blades) in one sled.
 
-The Yosemite-V3 system is in mass production. Meta, Intel and partners
+The Yosemite-V3 system is in mass production. Facebook, Intel and partners
 jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
 solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
 OSF solution reached production quality for some use cases in July, 2021.
@@ -196,9 +187,6 @@ and [u-root] as initramfs.
 [OCP]: https://www.opencompute.org
 [Delta Lake server design spec]: https://www.opencompute.org/documents/delta-lake-1s-server-design-specification-1v05-pdf
 [Yosemite-V3 design spec]: https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf
-[The OCP blog]: https://www.opencompute.org/blog/open-system-firmware-for-ocp-server-deltalake-is-published
-[The Wiwynn Press Release]: https://www.prnewswire.com/news-releases/wiwynn-successfully-implemented-open-system-firmware-on-its-ocp-yosemite-v3-server-301417374.html?tc=eml_cleartime
-[The Wiwynn's Yosemite-V3 product in OCP market place]: https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server
 [osf-builder]: https://github.com/facebookincubator/osf-builder
 [OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/prodrive/hermes.md

@@ -49,6 +49,6 @@ The board features:
 ## Extra links
 
 [flashrom]: https://flashrom.org/Flashrom
-[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
 [Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
 [AST2500]: https://www.aspeedtech.com/products.php?fPath=20&rId=440

Documentation/mainboard/starlabs/common/flashing.md

@@ -1,71 +0,0 @@
-# Flashing with fwupd
-
-#### **Requirements:**
-
-* fwupd version 1.5.6 or later
-* The battery must be charged to at least 30%
-* The charger must be connected (either USB-C or DC Jack)
-* BIOS Lock must be disabled
-* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+)
-
-**fwupd 1.5.6 or later**
-To check the version of **fwupd** you have installed, open a terminal window and enter the below command:
-
-```
-fwupdmgr --version
-```
-
-This will show the version number. **1.5.6** or greater will work.
-![fwupd version](fwupdVersion.png)
-On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
-
-```
-sudo add-apt-repository ppa:starlabs/ppa
-sudo apt update
-sudo apt install fwupd
-```
-
-On Manjaro:
-
-```
-sudo pacman -Sy fwupd-git flashrom-starlabs
-```
-
-Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB.
-
-**Disable BIOS Lock**
-BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock:
-
-1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings.
-2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
-3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
-
-![Disable BIOS Lock](BiosLock.jpg)
-
-4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
-
-#### **Switching Branch**
-
-Switching branch refers to changing from AMI firmware to coreboot, or vice versa.
-
-First, check for new firmware files with the below terminal command:
-
-```
-fwupdmgr refresh --force
-```
-
-Then, to change branch, enter the below terminal command:
-
-```
-fwupdmgr switch-branch
-```
-
-You can then select which branch you would like to use, by typing in the corresponding number:
-![Switch Branch](SwitchBranch.png)
-You will be prompted to confirm, press `y` to continue or `n` to cancel.
-
-Once the switch has been completed, you will be prompted to restart.
-
-The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using.
-
-You can switch branch at any time.

Documentation/mainboard/starlabs/labtop_cml.md

@@ -1,87 +0,0 @@
-# Star LabTop Mk IV
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-10710U (Comet Lake)
-    - Intel i3-10110U (Comet Lake)
-- EC
-    - ITE IT8987E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 620
-    - GOP driver is recommended, VBT is provided
-    - eDP 13-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 16GB on-board *1
-- Networking
-    - AX201 CNVi WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC256
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1280x720 CCD camera
-    - USB 3.1 Gen 2 Type-C (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c`
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | 25Q128JVSQ |
-+---------------------+------------+
-| Size                | 16 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glk.md

@@ -1,83 +0,0 @@
-# StarLite Mk III
-
-## Specs
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel N5000 (Gemini Lake)
-- EC
-    - ITE IT8987E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 605
-    - GOP driver is recommended, VBT is provided
-    - eDP 11.6-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 8GB on-board
-- Networking
-    - 9462 CNVi WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC269
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 SATA SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 640x480 CCD camera
-    - USB 3.1 Gen 1 Type-C (left)
-    - USB 3.1 Gen 1 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Gigadevice |
-+---------------------+------------+
-| Model               | GD25LQ64(B)|
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glkr.md

@@ -1,82 +0,0 @@
-# StarLite Mk III
-
-## Specs
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel N5030 (Gemini Lake Refresh)
-- EC
-    - Nuvoton NPCE985P/G
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 605
-    - GOP driver is recommended, VBT is provided
-    - eDP 11.6-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 8GB on-board
-- Networking
-    - 9461 CNVi WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC269
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 SATA SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1200x1600 CCD camera
-    - USB 3.1 Gen 1 Type-C (left)
-    - USB 3.1 Gen 1 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* IFWI Image (ifwi.rom)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Gigadevice |
-+---------------------+------------+
-| Model               | GD25LQ64(B)|
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -1,86 +0,0 @@
-# StarBook Mk V
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-1165G7 (Tiger Lake)
-    - Intel i3-1110G4 (Tiger Lake)
-- EC
-    - ITE IT5570E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel® Iris® Xe Graphics
-    - GOP driver is recommended, VBT is provided
-    - eDP 14-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 2 x DDR4 SODIMM
-- Networking
-    - AX201 2230 WiFi / Bluetooth
-- Sound
-    - Realtek ALC256
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1280x720 CCD camera
-    - Thunderbolt 4.0 (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-    - USB 2.0 Type-A (right)
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | 25Q128JVSQ |
-+---------------------+------------+
-| Size                | 16 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/supermicro/x10slm-f.md

@@ -42,7 +42,7 @@ Now, run `make` to build the coreboot image.
 
 ```eval_rst
 In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
+:doc:`../../flash_tutorial/index`.
 ```
 
 ### Internal programming

Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md

@@ -56,6 +56,6 @@ These issues apply to all boards. Have a look at the board-specific issues, too.
 [Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151
 [OpenBMC]: https://www.openbmc.org/
 [flashrom]: https://flashrom.org/Flashrom
-[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
 [Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
 [AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376

Documentation/mainboard/supermicro/x9sae.md

@@ -41,9 +41,10 @@ first, otherwise ME may write something back and break the firmware you write.
 The following command may be used to flash coreboot. (To do so, linux kernel
 could be started with `iomem=relaxed` or unload the `lpc_ich` kernel module)
 
-Now you can [flash internally]. It is recommended to flash only the `bios`
-region (use `--ifd -i bios -N` flashrom arguments), in order to minimize the
-chances of messing something up in the beginning.
+Now you can [flash internally](/flash_tutorial/int_flashrom.md). It is
+recommended to flash only the `bios` region (use `--ifd -i bios -N` flashrom
+arguments), in order to minimize the chances of messing something up in the
+beginning.
 
 The flash chip is a SOIC-8 SPI flash, and may be socketed, so it's also easy
 to do in-system programming, or remove and flash externally if it is socketed.
@@ -105,4 +106,3 @@ seems that it shall not appear on X9SAE even if it is defined.
 [X9SAE-V]:  https://www.supermicro.com/products/motherboard/xeon/c216/x9sae-v.cfm
 [W25Q128FVSG]: https://static.chipdip.ru/lib/093/DOC001093213.pdf
 [flashrom]: https://flashrom.org/Flashrom
-[flash internally]: ../../tutorial/flashing_firmware/int_flashrom.md

Documentation/mainboard/ti/beaglebone-black.md

@@ -127,5 +127,5 @@ ROM.
   hang on a bad SD card or when the SD card is removed during boot.
 
 
-[Beaglebone Black]: https://beagleboard.org/black
-[U-Boot Falcon mode]: https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon
+[Beaglebone Black]: https://beagleboard.org/black [U-Boot Falcon mode]:
+https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon

Documentation/northbridge/intel/sandybridge/me_cleaner.md

@@ -81,4 +81,4 @@ Make sure to include all partitions into the ROM:
 * ME
 * BIOS
 
-[external programmer]: ../../../tutorial/flashing_firmware/index.md
+[external programmer]: ../../../flash_tutorial/index.md

Documentation/releases/checklist.md

@@ -1,7 +1,3 @@
-```eval_rst
-:orphan:
-```
-
 # coreboot Release Process
 
 This document describes our release process and all prerequisites to implement

Documentation/releases/coreboot-4.15-relnotes.md

@@ -25,7 +25,7 @@ New mainboards
 * Google nipperkin
 * Lenovo w541
 * Siemens mc_ehl
-* Supermicro x9sae
+* SuperMicro x9sae
 * System76 addw1
 * System76 addw2
 * System76 bonw14

Documentation/releases/coreboot-4.16-relnotes.md

@@ -1,340 +1,19 @@
-coreboot 4.16
-========================================================================
+Upcoming release - coreboot 4.16
+================================
 
-The 4.16 release was done on February 25th, 2022.
+The 4.16 release is planned for February, 2022.
 
-Since 4.15 there have been more than 1770 new commits by more than 170
-developers.  Of these, more than 35 contributed to coreboot for the
-first time.
+We are increasing the frequency of releases in order to enable others to release quarterly on
+a fresher version of coreboot.
 
-Welcome to the project!
+Update this document with changes that should be in the release notes.
 
-Thank you to all the developers who continue to make coreboot the
-great open source firmware project that it is.
-
-New mainboards:
----------------
-* Acer Aspire VN7-572G
-* AMD Chausie
-* ASROCK H77 Pro4-M
-* ASUS P8Z77-M
-* Emulation QEMU power9
-* Google Agah
-* Google Anahera4ES
-* Google Banshee
-* Google Beadrix
-* Google Brya4ES
-* Google Crota
-* Google Dojo
-* Google Gimble4ES
-* Google Herobrine_Rev0
-* Google Kingler
-* Google Kinox
-* Google Krabby
-* Google Moli
-* Google Nereid
-* Google Nivviks
-* Google Primus4ES
-* Google Redrix4ES
-* Google Skyrim
-* Google Taeko4ES
-* Google Taniks
-* Google Vell
-* Google Volmar
-* Intel Alderlake-N RVP
-* Prodrive Atlas
-* Star Labs Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
-* System76 gaze16 3050
-* System76 gaze16 3060
-* System76 gaze16 3060-b
-
-Removed mainboards:
--------------------
-* Google ->  Corsola
-* Google ->  Nasher
-* Google ->  Stryke
-
-Added processors:
------------------
-* src/cpu/power9
-* src/soc/amd/sabrina
-
-Submodule Updates
------------------
-* /3rdparty/amd_blobs (6 commits)
-* /3rdparty/arm-trusted-firmware (965 commits)
-* /3rdparty/blobs (30 commits)
-* /3rdparty/chromeec (2212 commits)
-* /3rdparty/intel-microcode (1 commits)
-* /3rdparty/qc_blobs (13 commits)
-* /3rdparty/vboot (44 commits)
-
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the v4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the v4
-allocator.
-
-Plans for Code Deprecation
---------------------------
-As of release 4.18 (November 2022) we plan to deprecate LEGACY_SMP_INIT.
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.
-
-A few things are lacking in PARALLEL_MP init:
-- Support for !CONFIG_SMP on single core systems. It's likely easy to
-  extend PARALLEL_MP or write some code that just does CPU detection on
-  the BSP CPU.
-- Support SMM in the legacy ASEG (0xa0000 - 0xb0000) region. A POC
-  showed that it's not that hard to do with PARALLEL_MP
-  https://review.coreboot.org/c/coreboot/+/58700
-
-No platforms in the tree have any hardware limitations that would block
-migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
 
 Significant changes
 -------------------
-This is, of course, not a complete list of all changes in the 4.16
-coreboot release, but a sampling of some of the more interesting and
-significant changes.
 
-### Option to disable Intel Management Engine
-Disable the Intel (Converged Security) Management Engine ((CS)ME) via
-HECI based on Intel Core processors from Skylake to Alder Lake. State is
-set based on a CMOS value of `me_state`. A value of `0` will result in a
-(CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
-state of `3` (disabled). For an example CMOS layout and more info, see
-[cse.c](../../src/soc/intel/common/block/cse/cse.c).
-
-
-### Add [AMD] apcb_v3_edit tool
-apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
-up to 16 SPDs into an existing APCB. The APCB must have a magic number
-at the top of each SPD slot.
-
-
-### Allow enable/disable ME via CMOS
-Add .enable method that will set the CSME state. The state is based on
-the new CMOS option me_state, with values of 0 and 1. The method is very
-stable when switching between different firmware platforms.
-
-This method should not be used in combination with USE_ME_CLEANER.
-
-State 1 will result in:
-ME: Current Working State   : 4
-ME: Current Operation State : 1
-ME: Current Operation Mode  : 3
-ME: Error Code              : 2
-
-State 0 will result in:
-ME: Current Working State   : 5
-ME: Current Operation State : 1
-ME: Current Operation Mode  : 0
-ME: Error Code              : 0
-
-
-### Move LAPIC configuration to MP init
-Implementation for setup_lapic() did two things -- call enable_lapic()
-and virtual_wire_mode_init().
-
-In PARALLEL_MP case enable_lapic() was redundant as it was already
-executed prior to initialize_cpu() call.  For the !PARALLEL_MP case
-enable_lapic() is added to AP CPUs.
-
-
-### Add ANSI escape sequences for highlighting
-Add ANSI escape sequences to highlight a log line based on its loglevel
-to the output of "interactive" consoles that are meant to be displayed
-on a terminal (e.g. UART). This should help make errors and warnings
-stand out better among the usual spew of debug messages. For users whose
-terminal or use case doesn't support these sequences for some reason (or
-who simply don't like them), they can be disabled with a Kconfig.
-
-While ANSI escape sequences can be used to add color, minicom (the
-presumably most common terminal emulator for UART endpoints?) doesn't
-support color output unless explicitly enabled (via -c command line
-flag), and other terminal emulators may have similar restrictions, so in
-an effort to make this as widely useful by default as possible I have
-chosen not to use color codes and implement this highlighting via
-bolding, underlining and inverting alone (which seem to go through in
-all cases). If desired, support for separate color highlighting could be
-added via Kconfig later.
-
-
-### Add cbmem_dump_console
-This function is similar to cbmem_dump_console_to_uart except it uses
-the normally configured consoles. A console_paused flag was added to
-prevent the cbmem console from writing to itself.
-
-
-### Add coreboot-configurator
-A simple GUI to change CMOS settings in coreboot's CBFS, via the
-nvramtool utility.  Testing on Debian, Ubuntu and Manjaro with coreboot
-4.14+, but should work with any distribution or coreboot release that
-has an option table. For more info, please check the
-[README](https://web.archive.org/web/20220225194308/https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/coreboot-configurator/README.md).
-
-
-### Update live ISO configs to NixOS 21.11
-Update configs so that they work with NixOS 21.11. Drop `iasl` package
-since it was replaced with `acpica-tools`.
-
-
-### Move to U-Boot v2021.10
-Move to building the latest U-Boot.
-
-
-### Support systems with >128 cores
-Each time the spinlock is acquired a byte is decreased and then the
-sign of the byte is checked. If there are more than 128 cores the sign
-check will overflow. An easy fix is to increase the word size of the
-spinlock acquiring and releasing.
-
-
-### Add [samsung] sx9360 [proximity sensor] driver
-Add driver for setting up Semtech sx9360 SAR sensor.
-The driver is based on sx9310.c. The core of the driver is the same, but
-the bindings are slightly different.
-
-Registers are documented [in the kernel tree:](https://web.archive.org/web/20220225182803/https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/)
-Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
-
-
-### Add driver for Genesys Logic [SD Controller] GL9750
-The device is a PCIe Gen1 to SD 3.0 card reader controller to be
-used in the Chromebook. The datasheet name is GL9750S and the revision
-is 01.
-
-The patch disables ASPM L0s.
-
-
-### Add support for Realtek RT8125
-The Realtek RT8168 and RT8125 have a similar programming interface,
-therefore add the PCI device ID for the RT8125 into driver for support.
-
-
-### Add Fibocom 5G WWAN ACPI support
-Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
-PXSX._RST is invoked on driver removal.
-
-build dependency:
-  soc/intel/common/block/pcie/rtd3
-
-This driver will use the rtd3 methods for the same parent in the device
-tree. The rtd3 chip needs to be added on the same root port in the
-devicetree separately.
-
-
-### Fix bug in vr_config
-The `cpu_get_power_max()` function returns the TDP in milliwatts, but
-the vr_config code interprets the value in watts. Divide the value by
-1000 to fix this.
-
-This also fixes an integer overflow when `cpu_get_power_max()` returns
-a value greater than 65535 (UINT16_MAX).
-
-
-### Make mixed topology work
-When using a mixed memory topology with DDR4, it's not possible to boot
-when no DIMMs are installed, even though memory-down is available. This
-happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
-available. Relax the length check when no DIMMs are present to overcome
-this problem.
-
-
-### Add FSP 2.3 support
-FSP 2.3 specification introduces following changes:
-
-1. FSP_INFO_HEADER changes
-   Updated SpecVersion from 0x22 to 0x23
-   Updated HeaderRevision from 5 to 6
-   Added ExtendedImageRevision
-   FSP_INFO_HEADER length changed to 0x50
-
-2. Added FSP_NON_VOLATILE_STORAGE_HOB2
-
-Following changes are implemented in the patch to support FSP 2.3:
-
-- Add Kconfig option
-- Update FSP build binary version info based on ExtendedImageRevision
-  field in header
-- New NV HOB related changes will be pushed as part of another patch
-
-
-### Join hash calculation for verification and measurement
-This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT
-is enabled from the lookup step into the code where a file is actually
-loaded or mapped from flash. This has the advantage that CBFS routines
-which just look up a file to inspect its metadata (e.g. cbfs_get_size())
-do not cause the file to be measured twice. It also removes the existing
-inefficiency that files are loaded twice when measurement is enabled
-(once to measure and then again when they are used). When CBFS
-verification is enabled and uses the same hash algorithm as the TPM, we
-are even able to only hash the file a single time and use the result for
-both purposes.
-
-
-### Skip FSP Notify APIs
-Alder Lake SoC deselects Kconfigs as below:
-- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
-- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
-to skip FSP notify APIs (Ready to boot and End of Firmware) and make
-use of native coreboot driver to perform SoC recommended operations
-prior booting to payload/OS.
-
-Additionally, created a helper function `heci_finalize()` to keep HECI
-related operations separated for easy guarding again config.
-
-TODO: coreboot native implementation to skip FSP notify phase API (post
-pci enumeration) is still WIP.
-
-
-### Add support for PCIe Resizable BARs
-Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
-indicates support for "Resizable BARs" via a PCIe extended capability.
-
-When support this capability is indicated by the device, the size of
-each BAR is determined in a different way than the normal "moving
-bits" method. Instead, a pair of capability and control registers is
-allocated in config space for each BAR, which can be used to both
-indicate the different sizes the device is capable of supporting for
-the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
-to also inform the device of the size that the allocator actually
-reserved for the MMIO range.
-
-This patch adds a Kconfig for a mainboard to select if it knows that it
-will have a device that requires this support during PCI enumeration.
-If so, there is a corresponding Kconfig to indicate the maximum number
-of bits of address space to hand out to devices this way (again, limited
-by what devices can support and each individual system may want to
-support, but just like above, this number can range from 20 to 63) If
-the device can support more bits than this Kconfig, the resource request
-is truncated to the number indicated by this Kconfig.
+### Add significant changes here

Documentation/releases/coreboot-4.17-relnotes.md

@@ -1,19 +0,0 @@
-Upcoming release - coreboot 4.17
-================================
-
-The 4.17 release is planned for May, 2022.
-
-We are continuing the quarterly release cadence in order to enable others to
-release quarterly on a fresher version of coreboot.
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-
-Significant changes
--------------------
-
-### Add significant changes here

Documentation/releases/index.md

@@ -1,37 +1,30 @@
-# Release notes
+Release notes for previous releases
+===================================
 
-## Upcoming release
+* [4.1 - July 2015](coreboot-4.1-relnotes.md)
+* [4.2 - October 2015](coreboot-4.2-relnotes.md)
+* [4.3 - January 2016](coreboot-4.3-relnotes.md)
+* [4.4 - May 2016](coreboot-4.4-relnotes.md)
+* [4.5 - October 2016](coreboot-4.5-relnotes.md)
+* [4.6 - April 2017](coreboot-4.6-relnotes.md)
+* [4.7 - January 2018](coreboot-4.7-relnotes.md)
+* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
+* [4.9 - December 2018](coreboot-4.9-relnotes.md)
+* [4.10 - July 2019](coreboot-4.10-relnotes.md)
+* [4.11 - November 2019](coreboot-4.11-relnotes.md)
+* [4.12 - May 2020](coreboot-4.12-relnotes.md)
+* [4.13 - November 2020](coreboot-4.13-relnotes.md)
+* [4.14 - May 2021](coreboot-4.14-relnotes.md)
+* [4.15 - November 2021](coreboot-4.15-relnotes.md)
 
-Please add to the release notes as changes are added:
-* [4.17 - May 2022](coreboot-4.17-relnotes.md)
-
-The [checklist] contains instructions to ensure that a release covers all
+The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
 names etc.
 
-For release related communications consider using a [template] so everything
-important is taken care of.
+* [checklist](checklist.md)
 
+Upcoming release
+----------------
 
-## Previous releases
-
+Please add to the release notes as changes are added:
 * [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
-* [4.15 - November 2021](coreboot-4.15-relnotes.md)
-* [4.14 - May 2021](coreboot-4.14-relnotes.md)
-* [4.13 - November 2020](coreboot-4.13-relnotes.md)
-* [4.12 - May 2020](coreboot-4.12-relnotes.md)
-* [4.11 - November 2019](coreboot-4.11-relnotes.md)
-* [4.10 - July 2019](coreboot-4.10-relnotes.md)
-* [4.9 - December 2018](coreboot-4.9-relnotes.md)
-* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
-* [4.7 - January 2018](coreboot-4.7-relnotes.md)
-* [4.6 - April 2017](coreboot-4.6-relnotes.md)
-* [4.5 - October 2016](coreboot-4.5-relnotes.md)
-* [4.4 - May 2016](coreboot-4.4-relnotes.md)
-* [4.3 - January 2016](coreboot-4.3-relnotes.md)
-* [4.2 - October 2015](coreboot-4.2-relnotes.md)
-* [4.1 - July 2015](coreboot-4.1-relnotes.md)
-
-
-[checklist]: checklist.md
-[template]: templates.md

Documentation/releases/templates.md

@@ -1,87 +0,0 @@
-```eval_rst
-:orphan:
-```
-
-# Communication templates related to release management
-
-## Deprecation notices
-
-Deprecation notices are part of release notes to act as a warning: at some
-point in the future some part of coreboot gets removed. That point must be
-at least 6 months after the release of the notice and it must be right after
-some release: That is, the specified release must still contain the part in
-question while one git commit later it might be removed.
-
-The usual reason is progress: Infrastructure module X has been replaced by
-infrastructure module X+1. Removing X helps keep the sources manageable
-and likely opens opportunities to improve the codebase even more.
-Sometimes everything using some module has been converted to its successor
-already and it's natural for such modules to be removed. Even then it might
-be useful to add an entry to the release notes to make everybody aware of
-such a change, for maintainers of incomplete boards that they might keep in
-their local trees and also to give credit to the developers of that change.
-
-However this template isn't about such cases. Sometimes the tree contains
-mainboards that rely on X and can't be easily migrated to X+1, often because
-no active developer has access to these mainboards, and that is where this
-type of deprecation notice comes in:
-
-A deprecation notice shall outline what is being removed, when it is planned
-for removal (always directly _after_ a future release so it remains clear when
-something is part of coreboot and when it isn't anymore) and which devices
-would be affected at the time of writing. Since past deprecation notices have
-been read as "we plan to remove mainboards A, B, and C", sparking outrage
-with the devoted users of A, B, or C, some care is necessary to make clear
-which parts are slated for removal and which parts are merely consequences
-if no action is taken. Or put differently: It should be obvious that besides
-the deprecation plan, there is a call to action to save a couple of devices
-from becoming officially unsupported.
-
-As such, consider the following template when announcing a deprecation:
-
-### The Thing to remove
-
-A short description of the Thing slated for removal.
-
-A short rationale why it's being removed (e.g. new and better Thing exists
-in parallel; new Thing already demonstrated to work in this many releases;
-removing Thing enables this or that improvement)
-
-Timeline: Announced here, Thing will be removed right after the release X
-months out (where X >= 6)
-
-#### Call to action
-
-Removing Thing requires work on a number of (boards, chipsets, …) that didn't
-make the switch yet. The work approximately looks like this: (e.g. pointers to
-commits where a board has been successfully migrated from Thing to new Thing).
-
-Working on migrating away from Thing involves (hardware components, coreboot
-systems, …) 1, 2, and 3. It's difficult to do on the remaining devices because
-...
-
-Parts of the tree that need work to become independent of Thing.
- - chipset A
-   - board A1
-   - board A2
- - chipset B
-   - board B1
-
-We prefer to move them along, but if we don't see any maintenance in our tree
-we'll have to assume that there's no more interest in these platforms. As a
-consequence these devices either have to work without Thing by the removal
-date or they will be removed together with Thing. (side note: these removals
-aren't the law, so if there's work in progress to move boards off X and a
-roadmap that makes it probable to succeed, just not within the announced
-deprecation timeline, we can still decide to postpone the actual removal by
-one release. This needn't be put in the release notes themselves though or
-it might encourage people to look for simple escape hatches.)
-
-(If there are developers offering to write patches: )
-There are developers interested in helping move these forward but they can't
-test any changes for lack of equipment. If you have an affected device and
-can run tests on it, please reach out to developers α, β, and γ.
-
-(Otherwise maybe something more generic like this: )
-If you want to take this on, the coreboot developer community will try to
-help you: Reach out through one of our [forums](../community/forums.md).

Documentation/security/vboot/list_vboot.md

@@ -1,7 +1,6 @@
 # vboot-enabled devices
 
 ## AMD
-- Chausie
 - Majolica
 
 ## Clevo
@@ -30,37 +29,9 @@
 - Panther (ASUS Chromebox CN60)
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
-- Agah
-- Anahera
-- Anahera4ES
-- Brask
-- Brya 0
-- Brya4ES
-- Felwinter
-- Gimble
-- Gimble4ES
-- Kano
-- Nivviks
-- Nereid
-- Primus
-- Primus4ES
-- Redrix
-- Redrix4ES
-- Taeko
-- Taeko4ES
-- Taniks
-- Vell
-- Volmar
-- Banshee
-- Crota
-- Moli
-- Kinox
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
-- Dojo
 - Tomato
-- Kingler
-- Krabby
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -99,31 +70,31 @@
 - Nipperkin
 - Dewatt
 - Akemi (IdeaPad Flex 5/5i Chromebook)
-- Ambassador
-- Dooly
 - Dratini (HP Pro c640 Chromebook)
 - Duffy Legacy (32MB)
 - Duffy (ASUS Chromebox 4)
 - Faffy (ASUS Fanless Chromebox)
-- Genesis
 - Hatch
-- Helios (ASUS Chromebook Flip C436FA)
-- Helios_Diskswap
 - Jinlon (HP Elite c1030 Chromebook)
 - Kaisa Legacy (32MB)
 - Kaisa (Acer Chromebox CXI4)
-- Kindred (Acer Chromebook 712)
 - Kohaku (Samsung Galaxy Chromebook)
-- Moonbuggy
+- Kindred (Acer Chromebook 712)
+- Helios (ASUS Chromebook Flip C436FA)
 - Mushu
+- Palkia
 - Nightfury (Samsung Galaxy Chromebook 2)
 - Noibat (HP Chromebox G3)
-- Palkia
 - Puff
-- Scout
+- Helios_Diskswap
+- Stryke
 - Wyvern (CTL Chromebox CBx2)
+- Dooly
+- Ambassador
+- Genesis
+- Scout
+- Moonbuggy
 - Herobrine
-- Herobrine_Rev0
 - Senor
 - Piglin
 - Hoglin
@@ -194,6 +165,7 @@
 - Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
 - Snappy (HP Chromebook x360 11 G1 EE)
+- Nasher
 - Coral
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
@@ -206,7 +178,6 @@
 - Stout (Lenovo Thinkpad X131e Chromebook)
 - Bubs
 - Coachz
-- Gelarshie
 - Homestar
 - Kingoftown
 - Lazor
@@ -244,8 +215,6 @@
 - Alderlake-P RVP with Microchip EC
 - Alderlake-M RVP
 - Alderlake-M RVP with Chrome EC
-- Alderlake-N RVP
-- Alderlake-N RVP with Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
 - Coffeelake H SO-DIMM DDR4 RVP11

Documentation/soc/intel/fsp/index.md

@@ -2,18 +2,6 @@
 
 This section contains documentation about Intel-FSP in public domain.
 
-## Integration Guidelines
-
-Some guiding principles when working on the glue to integrate FSP into
-coreboot, e.g. on how to configure a board in devicetree when that affects
-the way FSP works:
-
-* It should be possible to replace FSP based boot with a native coreboot
-  implementation for a given chipset without touching the mainboard code.
-* The devicetree configures coreboot and part of what coreboot does with the
-  information is setting some FSP UPDs. The devicetree isn't supposed to
-  directly configure FSP.
-
 ## Bugs
 As Intel doesn't even list known bugs, they are collected here until
 those are fixed. If possible a workaround is described here as well.

Documentation/superio/nuvoton/nct5539d.md

@@ -1,9 +1,9 @@
-# NCT5539D Super I/O
+# NCT5539D SuperIO
 
-The Super I/O has the ID `0xd121` and the source can be found in
+The SuperIO has the ID `0xd121` and the source can be found in
 `src/superio/nuvoton/nct5539d/`.
 
 ## For developers
 
-The Super I/O generates ACPI using the
+The SuperIO generates ACPI using the
 [SSDT generator for generic SuperIOs](../common/ssdt.md).

Documentation/tutorial/index.md

@@ -4,4 +4,3 @@
 * [Part 2: Submitting a patch to coreboot.org](part2.md)
 * [Part 3: Writing unit tests](part3.md)
 * [Managing local additions](managing_local_additions.md)
-* [Flashing firmware](flashing_firmware/index.md)

Documentation/tutorial/part1.md

@@ -12,7 +12,7 @@ Download, configure, and build coreboot
 ### Step 1 - Install tools and libraries needed for coreboot
     $ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev
     $ sudo pacman -S base-devel curl git gcc-ada ncurses zlib
-    $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel patch
+    $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel
 
 ### Step 2 - Download coreboot source tree
     $ git clone https://review.coreboot.org/coreboot

Documentation/tutorial/part2.md

@@ -12,24 +12,37 @@ select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your
 username for the account will be the username of the account you used to
 sign-in with. (ex. your Google username).
 
-## Step 2a: Set up SSH keys
+## Step 2a: Set up RSA Private/Public Key
 
 If you prefer to use an HTTP password instead, skip to Step 2b.
 
-If you do not have an SSH key set up on your account already (as is the case
+For the most up-to-date instructions on how to set up SSH keys with Gerrit go to
+<https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/user-upload.html#configure_ssh>
+and follow the instructions there. Then, skip to Step 3.
+
+Additionally, that section of the Web site provides explanation on starting
+an ssh-agent, which may be particularly helpful for those who anticipate
+frequently uploading changes.
+
+If you instead prefer to have review.coreboot.org specific instructions,
+follow the steps below. Note that this particular section may have the
+most up-to-date instructions.
+
+If you do not have an RSA key set up on your account already (as is the case
 with a newly created account), follow the instructions below; otherwise,
 doing so could overwrite an existing key.
 
-In a terminal, run `ssh-keygen -t ed25519` and confirm the default path
-`.ssh/id_ed25519`.
+In the upper right corner, select your name and click on **Settings**.
+Select **SSH Public Keys** on the left-hand side.
+
+In a terminal, run `ssh-keygen` and confirm the default path `.ssh/id_rsa`.
 
 Make a passphrase -- remember this phrase. It will be needed whenever you use
-this public key. **Note:** You might want to use a short password, or
+this RSA Public Key. **Note:** You might want to use a short password, or
 forego the password altogether as you will be using it very often.
 
-Copy the content of `.ssh/id_ed25519.pub` (notice the ".pub" suffix
-as you need to send the public key) into the textbox "New SSH Key" at
-https://review.coreboot.org/settings/#SSHKeys and save it.
+Open `id_rsa.pub`, copy all contents and paste into the textbox under
+"Add SSH Public Key" in the https://review.coreboot.org webpage.
 
 ## Step 2b: Set up an HTTP Password
 
@@ -160,9 +173,7 @@ When you are done with your commit, run `git push` to push your commit to
 coreboot.org. **Note:** To submit as a private patch, use
 `git push origin HEAD:refs/for/master%private`. Submitting as a private patch
 means that your commit will be on review.coreboot.org, but is only visible to
-yourself and those you add as reviewers. This mode isn't perfect: Somebody who
-knows the commit ID can still fetch the change and everything it refers (e.g.
-parent commits).
+yourself and those you add as reviewers.
 
 This has been a quick primer on how to submit a change to Gerrit for review
 using git. You may wish to review the [Gerrit code review workflow

Documentation/util.md

@@ -12,8 +12,6 @@ settings. `Perl`
 * __apcb__ - AMD PSP Control Block tools
 	* _apcb_edit.py_ - This tool allows patching an existing APCB
 binary with specific SPDs and GPIO selection pins. `Python3`
-	* _apcb_v3_edit.py_ - This tool allows patching an existing APCB V3
-binary with specific SPDs. `Python3`
 * __archive__ - Concatenate files and create an archive `C`
 * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
 platforms `Go`

MAINTAINERS

@@ -141,9 +141,7 @@ AMD family 17h and 19h reference boards
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
-F:	src/mainboard/amd/chausie/
 F:	src/mainboard/amd/majolica/
 F:	src/mainboard/amd/mandolin/
 
@@ -221,18 +219,25 @@ F:	src/mainboard/clevo/
 
 FACEBOOK FBG1701 MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
-M:	Erik van den Bogaert <ebogaert@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/mainboard/facebook/fbg1701/
 
 FACEBOOK MONOLITH MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
-M:	Erik van den Bogaert <ebogaert@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/mainboard/facebook/monolith/
 
 
 
+GETAC P470 MAINBOARD
+M:	Patrick Georgi <patrick@georgi.software>
+S:	Maintained
+F:	src/mainboard/getac/p470/
+
+
+
 GIGABYTE GA-D510UD MAINBOARD
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
@@ -298,14 +303,6 @@ M:	Damien Zammit <damien@zamaudio.com>
 S:	Odd Fixes
 F:	src/mainboard/intel/d510mo/
 
-INTEL HARCUVAR_CRB MAINBOARD
-M:	Jeff Daly <jeffd@silicom-usa.com>
-M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
-M:	Suresh Bellampalli <suresh.bellampalli@intel.com>
-M:	Mariusz Szafranski <mariuszx.szafranski@intel.com>
-S:	Maintained
-F:	src/mainboard/intel/harcuvar/
-
 INTEL STRAGO MAINBOARD
 M:	Hannah Williams <hannah.williams@intel.com>
 S:	Supported
@@ -330,6 +327,7 @@ F:	src/mainboard/kontron/mal10/
 
 LENOVO MAINBOARDS
 M:	Alexander Couzens <lynxis@fe80.eu>
+M:	Patrick Rudolph <siro@das-labor.org>
 S:	Maintained
 F:	src/mainboard/lenovo/
 
@@ -403,7 +401,7 @@ F:	src/mainboard/pcengines/
 
 PORTWELL PQ-M107 MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
-M:	Erik van den Bogaert <ebogaert@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/mainboard/portwell/m107/
 
@@ -450,14 +448,6 @@ SIEMENS MC_xxxx MAINBOARDS
 M:	Werner Zeh <werner.zeh@siemens.com>
 S:	Maintained
 F:	src/mainboard/siemens/mc_apl1/
-F:	src/mainboard/siemens/mc_ehl/
-
-
-
-STAR LABS MAINBOARDS
-M:	Sean Rhodes <sean@starlabs.systems>
-S:	Maintained
-F:	src/mainboard/starlabs/
 
 
 
@@ -533,11 +523,6 @@ M:	Alexander Couzens <lynxis@fe80.eu>
 S:	Maintained
 F:	src/ec/lenovo/
 
-STARLABS EC
-M:	Sean Rhodes <sean@starlabs.systems>
-S:	Maintained
-F:	src/ec/starlabs/
-
 SYSTEM76 EC
 M:	Jeremy Soller <jeremy@system76.com>
 M:	Tim Crawford <tcrawford@system76.com>
@@ -582,6 +567,7 @@ F:	src/southbridge/amd/
 F:	src/include/cpu/amd/
 
 INTEL SUPPORT
+M:	Patrick Rudolph <siro@das-labor.org>
 S:	Maintained
 F:	src/vendorcode/intel/
 F:	src/cpu/intel/
@@ -591,6 +577,15 @@ F:	src/soc/intel/
 F:	src/drivers/intel/
 F:	src/include/cpu/intel/
 
+INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
+M:	Suresh Bellampalli <suresh.bellampalli@intel.com>
+M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
+M:	Michal Motyl <michalx.motyl@intel.com>
+M:	Mariusz Szafranski <mariuszx.szafranski@intel.com>
+S:	Maintained
+F:	src/mainboard/intel/harcuvar/
+F:	src/soc/intel/denverton_ns/
+
 INTEL FSP 1.1
 M:	Lee Leahy <leroy.p.leahy@intel.com>
 M:	Huang Jin <huang.jin@intel.com>
@@ -612,7 +607,6 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/cezanne/
 F:	src/vendorcode/amd/fsp/cezanne/
@@ -622,7 +616,6 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/common/
 
@@ -631,21 +624,10 @@ M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
 S:	Maintained
 F:	src/soc/amd/picasso/
 F:	src/vendorcode/amd/fsp/picasso/
 
-AMD Sabrina
-M:	Marshall Dawson <marshalldawson3rd@gmail.com>
-M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Raul E Rangel <rrangel@chromium.org>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-S:	Maintained
-F:	src/soc/amd/sabrina/
-F:	src/vendorcode/amd/fsp/sabrina/
-
 AMD Stoneyridge
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
@@ -670,14 +652,6 @@ S:	Maintained
 F:	/src/soc/intel/braswell/
 F:	/src/vendorcode/intel/fsp/fsp1_1/braswell/
 
-INTEL DENVERTON-NS SOC
-M:	Jeff Daly <jeffd@silicom-usa.com>
-M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
-M:	Suresh Bellampalli <suresh.bellampalli@intel.com>
-M:	Mariusz Szafranski <mariuszx.szafranski@intel.com>
-S:	Maintained
-F:	src/soc/intel/denverton_ns/
-
 INTEL TIGERLAKE SOC
 M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
@@ -745,6 +719,7 @@ F:	payloads/external/LinuxBoot/
 ################################################################################
 
 ABUILD
+M:	Patrick Georgi <patrick@georgi-clan.de>
 M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	util/abuild/
@@ -753,6 +728,7 @@ BOARD STATUS
 F:	util/board_status/
 
 BUILD SYSTEM
+M:	Patrick Georgi <patrick@georgi-clan.de>
 M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	Makefile
@@ -776,6 +752,7 @@ F:	.git*
 F:	/util/gitconfig
 
 LINT SCRIPTS
+M:	Patrick Georgi <patrick@georgi-clan.de>
 M:	Martin Roth <gaumless@gmail.com>
 S:	Supported
 F:	util/lint/
@@ -881,7 +858,7 @@ F:	src/security/tpm/
 
 SUPERIOS & SUPERIOTOOL
 M:	Felix Held <felix-coreboot@felixheld.de>
-S:	Odd Fixes
+S:	Maintained
 F:	src/superio/
 F:	util/superiotool/
 
@@ -899,7 +876,7 @@ F:	*.ld
 
 ELTAN VENDORCODE
 M:	Frans Hendriks <fhendriks@eltan.com>
-M:	Erik van den Bogaert <ebogaert@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/vendorcode/eltan/
 
@@ -913,7 +890,6 @@ TESTS
 M:	Jakub Czapiga <jacz@semihalf.com>
 S:	Maintained
 F:	tests/
-F:	payloads/libpayload/tests/
 
 MISSING: TIMERS / DELAYS
 
@@ -951,6 +927,7 @@ MISSING: SPI
 
 CODE OF CONDUCT
 M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
+M:	Patrick Georgi <patrick@coreboot.org>
 M:	Ronald Minnich <rminnich@coreboot.org>
 M:	Martin Roth <martin@coreboot.org>
 S:	Maintained

Makefile

@@ -20,6 +20,17 @@ VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib)
 COREBOOT_EXPORTS := COREBOOT_EXPORTS
 COREBOOT_EXPORTS += top src srck obj objutil objk
 
+# reproducible builds
+LANG:=C
+LC_ALL:=C
+TZ:=UTC0
+ifneq ($(NOCOMPILE),1)
+SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p')
+endif
+# don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system
+# are reproducible
+export LANG LC_ALL TZ SOURCE_DATE_EPOCH
+
 DOTCONFIG ?= $(top)/.config
 KCONFIG_CONFIG = $(DOTCONFIG)
 KCONFIG_AUTOADS := $(obj)/cb-config.ads
@@ -52,7 +63,6 @@ ifneq ($(V),1)
 ifneq ($(Q),)
 .SILENT:
 MAKEFLAGS += -s
-quiet_errors := 2>/dev/null
 endif
 endif
 
@@ -165,17 +175,6 @@ $(error $(xcompile) deleted because it's invalid. \
 	Restarting the build should fix that, or explain the problem)
 endif
 
-# reproducible builds
-LANG:=C
-LC_ALL:=C
-TZ:=UTC0
-ifneq ($(NOCOMPILE),1)
-SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p')
-endif
-# don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system
-# are reproducible
-export LANG LC_ALL TZ SOURCE_DATE_EPOCH
-
 ifneq ($(CONFIG_MMX),y)
 CFLAGS_x86_32 += -mno-mmx
 endif
@@ -193,7 +192,6 @@ strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
 real-all: real-target
 
 # must come rather early
-.SECONDARY:
 .SECONDEXPANSION:
 .DELETE_ON_ERROR:
 
@@ -470,10 +468,10 @@ doxyclean: doxygen-clean
 doxygen-clean:
 	rm -rf $(DOXYGEN_OUTPUT_DIR)
 
-clean-for-update: doxygen-clean
+clean-for-update: doxygen-clean clean-for-update-target
 	rm -rf $(obj) .xcompile
 
-clean: clean-for-update clean-utils clean-payloads
+clean: clean-for-update clean-target clean-utils
 	rm -f .ccwrap
 
 clean-cscope:

Makefile.inc

@@ -81,9 +81,8 @@ PHONY+= clean-abuild coreboot check-style build_complete
 # root source directories of coreboot
 subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
-subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))
-subdirs-y += $(wildcard src/northbridge/*/*)
-subdirs-y += $(filter-out src/superio/common,$(wildcard src/superio/*)) $(wildcard src/superio/*/*)
+subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
+subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*)
 subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*)
 subdirs-y += src/cpu src/vendorcode
 subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool
@@ -190,29 +189,29 @@ ramstage-generic-ccopts += -D__RAMSTAGE__
 ifeq ($(CONFIG_COVERAGE),y)
 ramstage-c-ccopts += -fprofile-arcs -ftest-coverage
 endif
+
 ifneq ($(UPDATED_SUBMODULES),1)
 # try to fetch non-optional submodules if the source is under git
-forgetthis:=$(if $(GIT),$(shell git submodule update --init $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init))
 # Checkout Cmocka repository
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka))
 ifeq ($(CONFIG_USE_BLOBS),y)
 # These items are necessary because each has update=none in .gitmodules.  They are ignored
 # until expressly requested and enabled with --checkout
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors)))
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
 ifeq ($(CONFIG_FSP_USE_REPO),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
 endif
 ifeq ($(CONFIG_USE_AMD_BLOBS),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs))
 endif
 ifeq ($(CONFIG_USE_QC_BLOBS),y)
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors)))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs))
 endif
 endif
 UPDATED_SUBMODULES:=1
 COREBOOT_EXPORTS += UPDATED_SUBMODULES
-
 endif
 
 postcar-c-deps:=$$(OPTION_TABLE_H)
@@ -261,24 +260,18 @@ endef
 # ResourceTemplate is the correct code.
 # As it's valid ASL, disable the warning.
 EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
-# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
-#	1) If _PRS is present, must have _CRS and _SRS
-#	2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
-#	3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
-#	4) If _SRS is present, probably should have a _DIS (Remark only)
-# A warning will be issued for each of these cases.
-# For existing ASL code, ignore this warnings
-IASL_MISSING_DEPENDENCY = 3141
+# Redundant offset remarks are not useful in any way and are masking useful
+# ones that might indicate an issue so it is better to hide them.
+REDUNDANT_OFFSET_REMARK = 2158
+# Ignore _HID & _ADR coexisting in Intel Lynxpoint ASL code.
+# See cb:38802
+# "Multiple types (Device object requires either a _HID or _ADR, but not both)"
+MULTIPLE_TYPES_WARNING = 3073
 
 IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK)
 
-ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
-	IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY)
-build_complete::
-	printf "*** WARNING: The ASL code for this platform is incomplete.  Please fix it. ***\n"
-	printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
-	printf "*** If _SRS is present, must have _PRS and _CRS ***\n"
-	printf "*** If _DIS is present, must have _SRS, _PRS and _CRS ***\n"
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
+IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING)
 endif
 
 IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
@@ -287,9 +280,6 @@ define asl_template
 $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml
 $(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw
 $(CONFIG_CBFS_PREFIX)/$(1).aml-compression = none
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-$(CONFIG_CBFS_PREFIX)/$(1).aml-align = 64
-endif
 cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml
 -include $(obj)/$(1).d
 $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h
@@ -337,7 +327,7 @@ endef
 # arg1: C source file
 # arg2: binary file
 cbfs-files-processor-struct= \
-	$(eval $(2): $(1) $(obj)/build.h $(obj)/fmap_config.h $(KCONFIG_AUTOHEADER); \
+	$(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \
 		printf "    CC+STRIP   $(1)\n"; \
 		$(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) --param asan-globals=0 $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \
 		$(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \
@@ -451,7 +441,6 @@ ADAFLAGS_common += -pipe -g -nostdinc
 ADAFLAGS_common += -Wstrict-aliasing -Wshadow
 ADAFLAGS_common += -fno-common -fomit-frame-pointer
 ADAFLAGS_common += -ffunction-sections -fdata-sections
-ADAFLAGS_common += -fno-pie
 # Ada warning options:
 #
 #  a   Activate most optional warnings.
@@ -599,8 +588,6 @@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
 
 APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
 
-APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py
-
 CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage
 
 FUTILITY?=$(objutil)/futility/futility
@@ -673,6 +660,19 @@ decompressor-y += $(CONFIG_MEMLAYOUT_LD_FILE)
 clean-abuild:
 	rm -rf coreboot-builds
 
+clean-for-update-target: clean-payloads
+	rm -f $(obj)/ramstage?* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a
+	rm -rf $(obj)/bootblock?* $(obj)/romstage?* $(obj)/location.*
+	rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript
+	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot
+	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
+	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/dsdt.*
+	rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm
+
+clean-target:
+	rm -f $(obj)/coreboot*
+
 #######################################################################
 # Development utilities
 printcrt0s:
@@ -776,14 +776,11 @@ endif
 $(objcbfs)/%.bin: $(objcbfs)/%.raw.bin
 	cp $< $@
 
-$(objcbfs)/%.map: $(objcbfs)/%.debug
-	$(eval class := $(call find-class,$(@F)))
-	$(NM_$(class)) -n $< | sort > $(basename $@).map
-
-$(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/%.map
+$(objcbfs)/%.elf: $(objcbfs)/%.debug
 	$(eval class := $(call find-class,$(@F)))
 	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
 	cp $< $@.tmp
+	$(NM_$(class)) -n $@.tmp | sort > $(basename $@).map
 	$(OBJCOPY_$(class)) --strip-debug $@.tmp
 	$(OBJCOPY_$(class)) --add-gnu-debuglink=$< $@.tmp
 	mv $@.tmp $@
@@ -1100,10 +1097,6 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
 endif
 
-# coreboot.pre doesn't follow the standard Make conventions. It gets modified
-# by multiple rules, and thus we can't compute the dependencies correctly.
-$(shell rm -f $(obj)/coreboot.pre)
-
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc
 	$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)
@@ -1221,10 +1214,6 @@ cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
 $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)
 $(CONFIG_CBFS_PREFIX)/ramstage-type := stage
 $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)
-# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
-$(CONFIG_CBFS_PREFIX)/ramstage-align := 64
-endif
 
 cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
 $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)

configs/config.emulation_qemu_power9

@@ -1 +0,0 @@
-CONFIG_BOARD_EMULATION_QEMU_POWER9=y

configs/config.emulation_qemu_x86_i440fx_debug

@@ -8,4 +8,3 @@ CONFIG_DEBUG_PIRQ=y
 CONFIG_DEBUG_MALLOC=y
 CONFIG_DEBUG_BOOT_STATE=y
 CONFIG_DEBUG_ADA_CODE=y
-CONFIG_CPU_QEMU_X86_PARALLEL_MP=y

configs/config.facebook_fbg1701.mboot_vboot

@@ -1,5 +1,6 @@
 CONFIG_VENDOR_FACEBOOK=y
 CONFIG_BOARD_FACEBOOK_FBG1701=y
+CONFIG_ONBOARD_SAMSUNG_MEM=y
 CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000
 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
 CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-4c-04"

configs/config.google_trogdor.build_test

@@ -1,8 +0,0 @@
-# Config to build test some optional Kconfigs on an Arm platform
-CONFIG_USE_BLOBS=y
-CONFIG_USE_QC_BLOBS=y
-CONFIG_VENDOR_GOOGLE=y
-CONFIG_BOARD_GOOGLE_TROGDOR=y
-CONFIG_CBFS_VERIFICATION=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_PAYLOAD_NONE=y

configs/config.google_volteer.build_test_purposes

@@ -30,4 +30,3 @@ CONFIG_DEBUG_MALLOC=y
 CONFIG_DEBUG_CONSOLE_INIT=y
 CONFIG_DEBUG_SPI_FLASH=y
 CONFIG_DEBUG_BOOT_STATE=y
-CONFIG_CBFS_VERIFICATION=y

configs/config.prodrive_hermes

@@ -1,13 +0,0 @@
-# Settings used by Prodrive to build coreboot for the Hermes
-CONFIG_VENDOR_PRODRIVE=y
-CONFIG_BOARD_PRODRIVE_HERMES=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Techonologies B.V."
-CONFIG_POST_IO=y
-CONFIG_USE_LEGACY_8254_TIMER=y
-CONFIG_HERMES_USES_SPS_FIRMWARE=y
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_SMMSTORE=y
-CONFIG_SMMSTORE_V2=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y
-CONFIG_POST_DEVICE_LPC=y
-CONFIG_MAINBOARD_SERIAL_NUMBER="N/A"