mb/system76/tgl: Update VBTs to version 250

Commit 4c7e97b26a ("Update fsp submodule to upstream master branch")
included an update to the VBT from 240 to 250, breaking parsing of
existing VBTs.

After that commit, the VBT was parsed as (from gaze16-3060-b):

    [DEBUG]  PCI: 00:02.0 init
    [INFO ]  GMA: Found VBT in CBFS
    [INFO ]  GMA: Found valid VBT in CBFS
    [INFO ]  framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32
    [INFO ]                     x_res x y_res: 1024 x 768, size: 3145728 at 0xd0000000
    [DEBUG]  PCI: 00:02.0 init finished in 6 msecs

When the expected output is:

    [DEBUG]  PCI: 00:00:02.0 init
    [INFO ]  GMA: Found VBT in CBFS
    [INFO ]  GMA: Found valid VBT in CBFS
    [INFO ]  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
    [INFO ]                     x_res x y_res: 1920 x 1080, size: 8294400 at 0xd0000000
    [DEBUG]  PCI: 00:00:02.0 init finished in 6 msecs

Generate blobs for the new version using Intel Display Configuration
Tool (DisCon) v3.3, based on the existing 237 and 240 VBTs.

(For our edk2 payload, the UEFI GOP driver was updated to 17.0.1077.)

Tested on all affected systems:

- darp7
- galp5
- gaze16-3050
- gaze16-3060
- gaze16-3060-b
- lemp10
- oryp8

Tested:

- Boot splash displays on screen again
- Firmware setup menu is rendered, at correct resolution

Change-Id: I918356d9f660b985ee4408ef77544fbd071ab35f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Daniel Sutton <daniel@system76.com>
Tested-by: Jacob Kauffmann <jacob@system76.com>

.gitmodules

@@ -1,67 +1,70 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = https://review.coreboot.org/blobs.git
+	url = ../blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = https://review.coreboot.org/nvidia-cbootimage.git
+	url = ../nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = https://review.coreboot.org/vboot.git
+	url = ../vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = https://review.coreboot.org/arm-trusted-firmware.git
+	url = ../arm-trusted-firmware.git
+[submodule "3rdparty/chromeec"]
+	path = 3rdparty/chromeec
+	url = ../chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = https://review.coreboot.org/libhwbase.git
+	url = ../libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = https://review.coreboot.org/libgfxinit.git
+	url = ../libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = https://review.coreboot.org/fsp.git
+	url = ../fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = https://review.coreboot.org/opensbi.git
+	url = ../opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = https://review.coreboot.org/intel-microcode.git
+	url = ../intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = https://review.coreboot.org/ffs.git
+	url = ../ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = https://review.coreboot.org/amd_blobs
+	url = ../amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = https://review.coreboot.org/cmocka.git
+	url = ../cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = https://review.coreboot.org/qc_blobs.git
+	url = ../qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = https://review.coreboot.org/9esec-security-tooling.git
+	url = ../9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = https://review.coreboot.org/STM
+	url = ../STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = https://review.coreboot.org/goswid
+	url = ../goswid
 	branch = trunk
 [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
 	path = src/vendorcode/amd/opensil/genoa_poc/opensil
-	url = https://review.coreboot.org/opensil_genoa_poc.git
+	url = ../opensil_genoa_poc.git

AUTHORS

@@ -39,9 +39,7 @@ Alexandru Gagniuc
 Alexey Buyanov
 Alexey Vazhnov
 Alice Sell
-Alicja Michalska
 Allen-KH Cheng
-Alper Nebi Yasak
 Amanda Hwang
 American Megatrends International, LLC
 Amersel
@@ -64,7 +62,6 @@ Anna Karaś
 Annie Chen
 Anton Kochkov
 Ao Zhong
-Appukuttan V K
 Arashk Mahshidfar
 Arec Kao
 Ariel Fang
@@ -96,7 +93,6 @@ Bora Guvendik
 Boris Barbulovski
 Boris Mittelberg
 Brandon Breitenstein
-Brandon Weeks
 Brian Norris
 Bryant Ou
 Carl-Daniel Hailfinger
@@ -105,7 +101,6 @@ Caveh Jalali
 Cavium Inc.
 Chao Gui
 Chen-Tsung Hsieh
-Chen. Gang C
 Chia-Ling Hou
 Chien-Chih Tseng
 Chris Wang
@@ -133,7 +128,6 @@ Da Lao
 Daisuke Nojiri
 Damien Zammit
 Dan Callaghan
-Dan Campbell
 Daniel Campello
 Daniel Gröber
 Daniel Kang
@@ -187,7 +181,6 @@ Eltan B.V
 Eltan B.V.
 Elyes Haouas
 Eran Mitrani
-Eren Peng
 Eric Biederman
 Eric Lai
 Eric Peers
@@ -201,16 +194,13 @@ Evan Green
 Evgeny Zinoviev
 Fabian Groffen
 Fabian Kunkel
-Fabian Meyer
 Fabio Aiuto
 Fabrice Bellard
 Facebook, Inc.
-Fei Yan
 Felix Friedlander
 Felix Held
 Felix Singer
 Fengquan Chen
-Filip Lewiński
 Flora Fu
 Florian Laufenböck
 Francois Toguo Fotso
@@ -224,7 +214,7 @@ Free Software Foundation, Inc.
 Freescale Semiconductor, Inc.
 Furquan Shaikh
 Gaggery Tsai
-Gang C Chen
+Gang C Chen 
 Garmin Chang
 Gary Jennejohn
 George Trudeau
@@ -244,7 +234,6 @@ HardenedLinux
 Harsha B R
 Harshit Sharma
 Henry C Chen
-Herbert Wu
 Hewlett Packard Enterprise Development LP
 Hewlett-Packard Development Company, L.P.
 Himanshu Sahdev
@@ -297,7 +286,6 @@ Jason Zhao
 jason-ch chen
 Jason-jh Lin
 Jay Patel
-Jean Lucas
 Jeff Chase
 Jeff Daly
 Jeff Li
@@ -319,7 +307,6 @@ Jitao Shi
 Joe Pillow
 Joe Tessler
 Joel Kitching
-Joel Linn
 Joey Peng
 Johanna Schander
 John Su
@@ -338,7 +325,6 @@ Jordan Crouse
 Jörg Mische
 Joseph Smith
 Josie Nordrum
-Juan José García-Castro Crespo
 Julia Tsai
 Julian Schroeder
 Julian Stecklina
@@ -351,7 +337,6 @@ Kangheui Won
 Kapil Porwal
 Karol Zmyslowski
 Karthik Ramasubramanian
-Kei Hiroyoshi
 Keith Hui
 Keith Packard
 Kenneth Chan
@@ -382,11 +367,9 @@ Lawrence Chang
 Leah Rowe
 Lean Sheng Tan
 Lei Wen
-Lennart Eichhorn
 Lenovo Group Ltd
 Leo Chou
 Li-Ta Lo
-Li1 Feng
 Liam Flaherty
 Libra Li
 Libretrend LDA
@@ -414,7 +397,6 @@ Marc Bertens
 Marc Jones
 Marco Chen
 Marek Kasiewicz
-Marek Maślanka
 Marek Vasut
 Mario Scheithauer
 Marius Gröger
@@ -483,12 +465,10 @@ Myles Watson
 Nancy.Lin
 Naresh Solanki
 Nathan Lu
-Naveen R. Iyer
 Neill Corlett
 Network Appliance Inc.
 Nicholas Chin
 Nicholas Sielicki
-Nicholas Sudsgaard
 Nick Barker
 Nick Chen
 Nick Vaccaro
@@ -522,7 +502,6 @@ Paul Fagerburg
 Paul Menzel
 Paul2 Huang
 Paulo Alcantara
-Pavan Holla
 Pavel Sayekat
 Paz Zcharya
 PC Engines GmbH
@@ -541,7 +520,6 @@ Philipp Deppenwiese
 Philipp Hug
 Piotr Kleinschmidt
 Po Xu
-Poornima Tom
 Prasad Malisetty
 Prashant Malani
 Pratik Vishwakarma
@@ -551,7 +529,6 @@ Protectli
 Purism SPC
 Purism, SPC
 Qii Wang
-Qinghong Zeng
 Qualcomm Technologies, Inc.
 Quanta Computer INC
 Raihow Shi
@@ -595,7 +572,6 @@ Robinson P. Tryon
 Rockchip, Inc.
 Rocky Phagura
 Roger Lu
-Roger Wang
 Roja Rani Yarubandi
 Romain Lievin
 Roman Zippel
@@ -769,14 +745,12 @@ Wojciech Macek
 Wolfgang Denk
 Won Chung
 Wonkyu Kim
-Wuxy
-Xiang W
+Wuxy 
 Xin Ji
 Xixi Chen
 Xuxin Xiong
 YADRO
 Yan Liu
-Yang Wu
 Yann Collet
 Yaroslav Kurlaev
 YH Lin
@@ -793,7 +767,6 @@ Yuanliding
 Yuchen He
 Yuchen Huang
 Yunlong Jia
-Yuval Peress
 Zachary Yedidia
 Zanxi Chen
 Zhanyong Wang
@@ -803,11 +776,10 @@ Zhi7 Li
 Zhiqiang Ma
 Zhixing Ma
 Zhiyong Tao
-Zhongtian Wu
+zhongtian wu
 Zhuohao Lee
 Ziang Wang
 Zoey Wu
 Zoltan Baldaszti
 小田喜陽彦
-忧郁沙茶
 陳建宏

Documentation/Makefile

@@ -31,7 +31,8 @@ livesphinx: $(BUILDDIR)
 
 test:
 	@echo "Test for logging purposes - Failing tests will not fail the build"
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -k -f Makefile.sphinx html
+	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
+	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
 
 help:
 	@echo "all            - Builds all documentation targets"

Documentation/distributions.md

@@ -29,7 +29,7 @@ sealings are sent via encrypted email.
 
 ### NovaCustom laptops
 
-[NovaCustom](https://novacustom.com) sells configurable laptops with
+[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
 [Dasharo](https://dasharo.com/) coreboot based firmware on board, maintained by
 [3mdeb](https://3mdeb.com/). NovaCustom offers full GNU/Linux and Microsoft
 Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years

Documentation/getting_started/faq.md

@@ -84,8 +84,8 @@ the operating system.
 
 * U-boot, depthcharge, FILO, etc.
 
-There’s [https://doc.coreboot.org/payloads.html](https://doc.coreboot.org/payloads.html)
-with a list, although it’s not complete.
+There’s [https://doc.coreboot.org/payloads.html](https://doc.coreboot.org/payloads.
+html) with a list, although it’s not complete.
 
 
 ### What does coreboot leave in memory after it's done initializing the hardware?

Documentation/getting_started/kconfig.md

@@ -200,9 +200,9 @@ values to be set based on other values.
   visible in the front end.
 
 
-### Keywords
+## Keywords
 
-#### bool
+### bool
 
 The 'bool' keyword assigns a boolean type to a symbol. The allowable values for
 a boolean type are 'n' or 'y'. The keyword can be followed by an optional prompt
@@ -238,7 +238,7 @@ bool \[prompt\] \[if <expr>\]
 
 --------------------------------------------------------------------------------
 
-#### choice
+### choice
 
 This creates a selection list of one or more boolean symbols. For bools, only
 one of the symbols can be selected, and one will be be forced to be selected,
@@ -301,7 +301,7 @@ choice \[symbol\]
 
 --------------------------------------------------------------------------------
 
-#### comment
+### comment
 
 This keyword defines a line of text that is displayed to the user in the
 configuration frontend and is additionally written to the output files.
@@ -326,7 +326,7 @@ comment <prompt>
 
 --------------------------------------------------------------------------------
 
-#### config
+### config
 
 This is the keyword that starts a block defining a Kconfig symbol. The symbol
 modifiers follow the 'config' statement.
@@ -363,7 +363,7 @@ config <symbol>
 
 --------------------------------------------------------------------------------
 
-#### default
+### default
 
 The ‘default’ keyword assigns a value to a symbol in the case where no preset
 value exists, i.e. the symbol is not present and assigned in .config.  If there
@@ -403,7 +403,7 @@ default <expr> \[if <expr>\]
 
 --------------------------------------------------------------------------------
 
-#### def_bool
+### def_bool
 
 ‘def_bool’ is similar to the 'bool' keyword in that it sets a symbol’s type to
 boolean. It lets you set the type and default value at the same time, instead
@@ -437,7 +437,7 @@ def_bool <expr> \[if <expr>\]
 
 --------------------------------------------------------------------------------
 
-#### depends on
+### depends on
 
 This defines a dependency for a menu entry, including symbols and comments.  It
 behaves the same as surrounding the menu entry with an if/endif block.  If the
@@ -466,28 +466,28 @@ depends on <expr>
 
 --------------------------------------------------------------------------------
 
-#### endchoice
+### endchoice
 
 This ends a choice block. See the 'choice' keyword for more information and an
 example.
 
 --------------------------------------------------------------------------------
 
-#### endif
+### endif
 
 This ends a block started by the 'if' keyword. See the 'if' keyword for more
 information and an example.
 
 --------------------------------------------------------------------------------
 
-#### endmenu
+### endmenu
 
 This ends a menu block. See the 'menu' keyword for more information and an
 example.
 
 --------------------------------------------------------------------------------
 
-#### help
+### help
 
 The 'help' keyword defines the subsequent block of text as help for a config or
 choice block. The help block is started by the 'help' keyword on a line by
@@ -519,7 +519,7 @@ help <help text>
 
 --------------------------------------------------------------------------------
 
-#### hex
+### hex
 
 This is another symbol type specifier, specifying an unsigned integer value
 formatted as hexadecimal.
@@ -555,7 +555,7 @@ hex <expr> \[if <expr>\]
 
 --------------------------------------------------------------------------------
 
-#### if
+### if
 
 The 'if' keyword is overloaded, used in two different ways. The first definition
 enables and disables various other keywords, and follows the other keyword
@@ -596,7 +596,7 @@ endif
 
 --------------------------------------------------------------------------------
 
-#### int
+### int
 
 A type setting keyword, defines a symbol as an integer, accepting only signed
 numeric values.  The values can be further restricted with the ‘range’ keyword.
@@ -632,7 +632,7 @@ int <expr> \[if <expr>\]
 
 --------------------------------------------------------------------------------
 
-#### mainmenu
+### mainmenu
 
 The 'mainmenu' keyword sets the title or title bar of the configuration front
   end, depending on how the configuration program decides to use it. It can only
@@ -652,7 +652,7 @@ mainmenu "coreboot configuration"
 
 --------------------------------------------------------------------------------
 
-#### menu
+### menu
 
 The 'menu' and 'endmenu' keywords tell the configuration front end that the
 enclosed statements are part of a group of related pieces.
@@ -699,7 +699,7 @@ endmenu
 
 --------------------------------------------------------------------------------
 
-#### prompt
+### prompt
 
 The 'prompt' keyword sets the text displayed for a config symbol or choice in
 configuration front end.
@@ -752,7 +752,7 @@ prompt <prompt> \[if <expr>\]
             prompt "Prompt value 2"
 --------------------------------------------------------------------------------
 
-#### range
+### range
 
 This sets the allowable minimum and maximum entries for hex or int type config
 symbols.
@@ -774,7 +774,7 @@ range <symbol> <symbol> \[if <expr>\]
 
 --------------------------------------------------------------------------------
 
-#### select
+### select
 
 The ‘select’ keyword is used within a bool type config block.  In coreboot (and
 other projects that don't use modules), the 'select' keyword can force an
@@ -818,7 +818,7 @@ select <symbol> \[if <expr>\]
 
 --------------------------------------------------------------------------------
 
-#### source
+### source
 
 The 'source' keyword functions much the same as an 'include' statement in c.
 This pulls one or more files into Kconfig at the location of the 'source'
@@ -877,7 +877,7 @@ statements that generate a list of all the platform names:
 
 --------------------------------------------------------------------------------
 
-#### string
+### string
 
 The last of the symbol type assignment keywords. 'string' allows a text value to
 be entered.
@@ -923,7 +923,7 @@ keyword later. See the prompt keyword for more notes.
 
 
 
-### Keywords not used in coreboot at the time of writing:
+## Keywords not used in coreboot at the time of writing:
 
 - allnoconfig_y:
 - defconfig_list
@@ -948,7 +948,7 @@ statements:
     #define SYMBOL NAME XXX
 
 
-#### Symbol types:
+##### Symbol types:
 - bool, int, and hex types -  Every symbol of one of these types created in the
   Kconfig tree is defined.  It doesn’t matter whether they’re in an if/endif
   block, or have a ‘depends on’ statement - they ALL end up being defined in
@@ -1168,19 +1168,19 @@ saved .config file. As always, a 'select' statement overrides any specified
 
 ## Kconfig Editor Highlighting
 
-### vim:
+#### vim:
 
 vim has syntax highlighting for Kconfig built in (or at least as a part of
 vim-common), but most editors do not.
 
 
-### ultraedit:
+#### ultraedit:
 
 https://github.com/martinlroth/wordfiles/blob/master/kconfig.uew
 
 
 
-### atom:
+#### atom:
 
 https://github.com/martinlroth/language-kconfig
 

Documentation/getting_started/writing_documentation.md

@@ -99,7 +99,7 @@ To reference documents use the TOC tree or inline RST code.
 Under Sphinx markdown tables are not supported. Therefore you can use following
 code block to write tables in reStructuredText and embed them into the markdown:
 
-    ```{eval-rst}
+    ```eval_rst
     +------------+------------+-----------+
     | Header 1   | Header 2   | Header 3  |
     +============+============+===========+
@@ -144,7 +144,7 @@ you'll see the following warning:
 You can import CSV files and let sphinx automatically convert them to human
 readable tables, using the following reStructuredText snipped:
 
-    ```{eval-rst}
+    ```eval_rst
     .. csv-table::
        :header: "Key", "Value"
        :file: keyvalues.csv

Documentation/index.md

@@ -139,45 +139,6 @@ Every now and then, coreboot is present in one way or another at
 [conferences](community/conferences.md). If you're around, come and
 say hello!
 
-## Blob policy in the coreboot project
-
-The goal of the coreboot project is to provide a FOSS firmware solution across
-multiple CPU architectures, such as ARM, x86, and RISC-V. While fully open
-source implementations for these architectures are encouraged and preferred,
-we understand that a fully open implementation whereby every firmware component
-is available as source code for modern platforms is not always feasible.
-Different reasons inhibit the availability of fully open implementations,
-including limited development resources, 3rd party license constraints of
-IP blocks, or a legacy mindset of the silicon vendors.
-
-It is important for the coreboot project to have support for modern CPU
-platforms in order to provide a viable alternative for proprietary firmware
-implementations. We do not have direct control over how hardware vendors design
-their products, however we can provide an attractive alternative to the
-expensive and complicated proprietary firmware model that exists today.
-For modern platforms, we are largely dependent on the silicon
-vendor to provide additional information on how to properly initialize the
-hardware, as the required datasheets are often only available with an NDA.
-Therefore, one possible way to have coreboot support for the latest platforms
-is binary code (aka, a blob) provided by the silicon vendor. While we do
-discourage this solution, it can be a door opener for coreboot’s support of a
-given platform and thus keep coreboot functional on modern platforms. It is
-clearly not the goal of the project to accept every blob a silicon vendor wishes
-to use without question. On the contrary, each new blob needs to be examined
-critically by the community, evaluating the need, risk, and alternative options.
-
-Wherever possible, introducing new blobs should be avoided. That said, there
-can be situations where a piece of code provided as a blob will enable the rest
-of the fully open source firmware stack on a brand new platform. If blocking
-this blob would lead to no support at all for the platform in question in
-coreboot, this situation needs to be examined carefully. While these kinds
-of discussion will be coordinated closely with the community (e.g. on the
-mailing list or dedicated meetings), ultimately it is up to the leadership to
-decide if there is no agreement between the community and the vendor pushing for
-the new blob. This decision will be communicated on the mailing list.
-Please see additionally
-[coreboot binary policy](https://github.com/coreboot/blobs/blob/master/README.md).
-
 ## Getting the source code
 
 coreboot is primarily developed in the

Documentation/mainboard/dell/e7240.md

@@ -1,83 +0,0 @@
-# Dell Latitude E7240
-
-This page is about the notebook [Dell Latitude E7240].
-
-## Release status
-
-Dell Latitude E7240 was released in 2013 and is now end of life.
-It can be bought from a secondhand market like Taobao or eBay.
-
-## Required proprietary blobs
-
-The following blobs are required to operate the hardware:
-1. mrc.bin
-2. Intel ME firmware
-
-Memory reference code in mrc.bin is used to initialize the Haswell platform.
-You need this blob to build a working coreboot image. Please read
-[mrc.bin](../../northbridge/intel/haswell/mrc.bin) for instructions on
-retrieving and using it.
-
-Intel ME firmware is in the flash chip. It is not needed when building coreboot.
-It can be extracted from the OEM firmware. You can also flash only the BIOS
-region to leave Intel ME firmware untouched.
-
-## Programming
-
-The laptop can be flashed internally under OEM firmware using [dell-flash-unlock].
-
-To flash with an external programmer, you need to remove the battery and the base cover.
-
-![Dell Latitude E7240 mainboard](e7240.webp)
-
-For more details have a look at the general [flashing tutorial].
-
-It is also possible to flash internally under coreboot.
-
-## Debugging
-
-The board can be debugged with EHCI debug. The EHCI debug port is next to the miniDP port.
-
-There's a serial port on dock, but it's not yet supported in coreboot.
-
-Schematic of this laptop can be found online. The board name is Compal LA-9431P.
-
-## Test status
-
-### Not working
-
-- EC ACPI
-- SD/MMC card reader (kernel reports "Timeout waiting for hardware cmd interrupt.")
-- No internal display before booting to OS when connected with a dock
-
-### Working
-
-- Integrated graphics init with libgfxinit
-- mSATA
-- WLAN
-- USB
-- Keyboard
-- Touchpad and the buttons on it
-- Dock: all USB ports, DisplayPort, eSATA
-- Internal flashing
-
-
-## Technology
-
-```{eval-rst}
-+------------------+-----------------------------+
-| CPU              | Intel Haswell-ULT           |
-+------------------+-----------------------------+
-| PCH              | Intel Lynx Point Low Power  |
-+------------------+-----------------------------+
-| EC               | SMSC MEC5075                |
-+------------------+-----------------------------+
-| Super I/O        | SMSC ECE5048                |
-+------------------+-----------------------------+
-| Coprocessor      | Intel Management Engine     |
-+------------------+-----------------------------+
-```
-
-[Dell Latitude E7240]: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7240-ultrabook/docs
-[dell-flash-unlock]: https://github.com/nic3-14159/dell-flash-unlock
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md

Documentation/mainboard/emulation/qemu-sbsa.md

@@ -1,42 +0,0 @@
-# QEMU SBSA emulator
-This page describes how to build and run ```coreboot``` for QEMU's sbsa-ref machine.
-The qemu-sbsa ```coreboot``` image acts as BL-3.3 for Arm Trusted Firmware (```TF-A```) and
-mainly takes care of setting up SMBIOS and ACPI tables, hence, in order to boot,
-you also need to supply a ```TF-A``` image.
-
-## Building TF-A
-
-You can build ```TF-A``` from source by fetching
-```
-https://github.com/ARM-software/arm-trusted-firmware
-```
-and building the qemu-sbsa platform
-```
-PLAT=qemu_sbsa
-```
-Upon entry, ```coreboot``` expects a FDT pointer in x0, so make sure to compile ```TF-A``` with
-```
-ARM_LINUX_KERNEL_AS_BL33=1
-```
-This will force ```TF-A``` to pass a pointer to the FDT in x0.
-
-## Building coreboot
-
-Simply select the qemu-sbsa board and, optionally, configure a payload. We recommend
-the ```leanefi``` payload. ```leanefi``` will setup a minimal set of UEFI services, just enough
-to boot into a linux kernel.
-
-## Running coreboot in QEMU
-
-Once you have obtained ```TF-A``` and ```coreboot``` images, launch qemu via
-
-```bash
-qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <path/to/TFA.fd> \
-                                                   -pflash <path/to/coreboot.rom>
-```
-
-## LBBR bootflow
-
-arm and 9elements worked together in order to create a LBBR compliant bootflow
-consisting of ```TF-A```, ```coreboot```, ```leanefi``` and ```LinuxBoot```. A proof of concept
-can be found here https://gitlab.arm.com/systemready/firmware-build/linuxboot/lbbr-coreboot-poc

Documentation/mainboard/hp/8560w.md

@@ -1,80 +0,0 @@
-# HP EliteBook 8560w
-
-This page describes how to run coreboot on the [HP EliteBook 8560w].
-
-## Required proprietary blobs
-
-- Intel Firmware Descriptor, ME and GbE firmware
-- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops)
-
-## Flashing instructions
-
-When running vendor firmware, external flashing is needed.
-
-HP EliteBook 8560w has an 8MiB SOIC-8 flash chip on the bottom of the
-mainboard. You just need to remove the service cover, and use an SOIC-8
-clip to read and flash the chip.
-
-![8560w_chip_location](8560w_flash.webp)
-
-```{eval-rst}
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Model               | MX25L6406E |
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | no         |
-+---------------------+------------+
-| Dual BIOS feature   | no         |
-+---------------------+------------+
-| In circuit flashing | yes        |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-```
-
-## Working
-
-- i7-2720QM, 8G+8G
-- Arch Linux boot from SeaBIOS payload
-- EHCI debug: the port is beside the eSATA port
-- SATA
-- eSATA
-- USB2 and USB3
-- keyboard
-- Gigabit Ethernet
-- WLAN
-- WWAN
-- VGA and DisplayPort
-- audio
-- EC ACPI
-- Using `me_cleaner`
-- dock: PS/2 keyboard, USB, DisplayPort
-- TPM
-- S3 suspend/resume
-
-## Technology
-
-```{eval-rst}
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| Super I/O        | SMSC LPC47n217                                   |
-+------------------+--------------------------------------------------+
-| EC               | SMSC KBC1126                                     |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/5071171

Documentation/mainboard/hp/pro_3500_series.md

@@ -14,7 +14,7 @@ therefore the automatic fan control will not increase the fan speed.
 
 ## Flashing coreboot
 
-```{eval-rst}
+```{eval_rst}
 +---------------------+-------------------------+
 | Type                | Value                   |
 +=====================+=========================+
@@ -82,7 +82,7 @@ until cleanly power cycled.
 
 ## Technology
 
-```{eval-rst}
+```{eval_rst}
 +------------------+--------------------------------------------------+
 | Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
 +------------------+--------------------------------------------------+

Documentation/mainboard/index.md

@@ -76,7 +76,6 @@ N130WU / N131WU <clevo/n130wu/index.md>
 ```{toctree}
 :maxdepth: 1
 
-Latitude E7240 <dell/e7240.md>
 OptiPlex 9010 SFF <dell/optiplex_9010.md>
 ```
 
@@ -90,7 +89,6 @@ The boards in this section are not real mainboards, but emulators.
 Spike RISC-V emulator <emulation/spike-riscv.md>
 QEMU RISC-V emulator <emulation/qemu-riscv.md>
 QEMU AArch64 emulator <emulation/qemu-aarch64.md>
-QEMU SBSA emulator <emulation/qemu-sbsa.md>
 QEMU x86 Q35 <emulation/qemu-q35.md>
 QEMU x86 PC <emulation/qemu-i440fx.md>
 QEMU POWER9 <emulation/qemu-power9.md>
@@ -142,7 +140,6 @@ HP Laptops with KBC1126 EC <hp/hp_kbc1126_laptops.md>
 HP Sure Start <hp/hp_sure_start.md>
 EliteBook 2170p <hp/2170p.md>
 EliteBook 2560p <hp/2560p.md>
-EliteBook 8560w <hp/8560w.md>
 EliteBook 8760w <hp/8760w.md>
 EliteBook Folio 9480m <hp/folio_9480m.md>
 EliteBook 820 G2 <hp/elitebook_820_g2.md>
@@ -330,7 +327,6 @@ LabTop Mk III <starlabs/labtop_kbl.md>
 LabTop Mk IV <starlabs/labtop_cml.md>
 StarLite Mk III <starlabs/lite_glk.md>
 StarLite Mk IV <starlabs/lite_glkr.md>
-StarLite Mk V <starlabs/lite_adl.md>
 StarBook Mk V <starlabs/starbook_tgl.md>
 StarBook Mk VI <starlabs/starbook_adl.md>
 Flashing devices <starlabs/common/flashing.md>

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -82,7 +82,7 @@ It is possible to reduce the Intel ME firmware size to free additional
 space for the `bios` region. This is usually referred to as *cleaning the ME* or
 *stripping the ME*.
 After reducing the Intel ME firmware size you must modify the original IFD,
-[split the resulting coreboot ROM](#splitting-the-corebootrom) and then write
+[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write
 each ROM using an [external programmer].
 Have a look at [me_cleaner] for more information.
 

Documentation/mainboard/lenovo/montevina_series.md

@@ -46,7 +46,7 @@ Now you need to patch the flash descriptor. You can either [modify the one from
 your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
 [use one from the coreboot repository](#using-checked-in-flash-descriptor-via-bincfg).
 
-### Modifying flash descriptor using ifdtool
+#### Modifying flash descriptor using ifdtool
 
 Pick the layout according to your chip size from the table below and save it to
 the `new_layout.txt` file:
@@ -88,7 +88,7 @@ $ mv flashregion_0_flashdescriptor.bin.new.new flashregion_0_flashdescriptor.bin
 
 Continue to the [Configuring coreboot](#configuring-coreboot) section.
 
-### Using checked-in flash descriptor via bincfg
+#### Using checked-in flash descriptor via bincfg
 
 There is a copy of an X200's flash descriptor checked into the coreboot
 repository. It is supposed to work for the T400/T500 as well. The descriptor
@@ -119,7 +119,7 @@ $ make gen-ifd-x200
 
 It will be saved to the `flashregion_0_fd.bin` file.
 
-### Configuring coreboot
+#### Configuring coreboot
 
 Now configure coreboot. You need to select correct chip size and specify paths
 to flash descriptor and gbe dump.

Documentation/mainboard/prodrive/hermes.md

@@ -49,6 +49,6 @@ The board features:
 ## Extra links
 
 [flashrom]: https://flashrom.org/Flashrom
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md
-[Intel FSP2.0]: ../../soc/intel/fsp/index.md
+[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md
+[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
 [AST2500]: https://www.aspeedtech.com/products.php?fPath=20&rId=440

Documentation/mainboard/starlabs/common/building.md

@@ -1,15 +1,15 @@
-# Building coreboot
+## Building coreboot
 
-## Preliminaries
+### Preliminaries
 
 Prior to building coreboot the following files are required:
 
-### StarBook series:
+#### StarBook series:
 * Intel Flash Descriptor file (descriptor.bin)
 * Intel Management Engine firmware (me.bin)
 * ITE Embedded Controller firmware (ec.bin)
 
-### StarLite series:
+#### StarLite series:
 * Intel Flash Descriptor file (descriptor.bin)
 * IFWI Image (ifwi.rom)
 
@@ -18,7 +18,7 @@ The files listed below are optional:
 
 These files exist in the correct location in the [StarLabsLtd/blobs](https://github.com/StarLabsLtd/blobs) repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
 
-## Build
+### Build
 
 The following commands will build a working image, where the last two words represent the
 series and processor i.e. `lite_glkr`:

Documentation/mainboard/starlabs/common/flashing.md

@@ -1,6 +1,6 @@
 # Flashing with fwupd
 
-## **Requirements:**
+#### **Requirements:**
 
 * fwupd version 1.5.6 or later
 * The battery must be charged to at least 30%
@@ -44,7 +44,7 @@ BIOS Lock must be disabled when switching from the standard AMI (American Megatr
 
 4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
 
-## **Switching Branch**
+#### **Switching Branch**
 
 Switching branch refers to changing from AMI firmware to coreboot, or vice versa.
 

Documentation/mainboard/starlabs/lite_adl.md

@@ -1,82 +0,0 @@
-# StarBook Mk V
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel N200 (Alder Lake)
-- EC
-    - ITE IT5570E
-    - USB-C PD Charger
-    - Suspend / resume
-- GPU
-    - Intel® Iris® Xe Graphics
-    - GOP driver is recommended, VBT is provided
-    - eDP 12.5-inch 2880x1920 or 2160x1440 LCD
-    - 2 x USB-C DisplayPort video
-- Memory
-    - 16GB on-board
-- Networking
-    - 9560 CNVi WiFi / Bluetooth
-- Sound
-    - Realtek ALC269-VB6
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 2 x 5MP CCD Camera
-    - 2 x USB 3.1 Gen 2 Type-C (right)
-
-## Building coreboot
-
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_byte_adl
-make
-```
-
-## Flashing coreboot
-
-```{eval-rst}
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | W25Q256.V  |
-+---------------------+------------+
-| Size                | 32 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-```
-
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md

@@ -61,6 +61,6 @@ These issues apply to all boards. Have a look at the board-specific issues, too.
 [Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151
 [OpenBMC]: https://www.openbmc.org/
 [flashrom]: https://flashrom.org/Flashrom
-[flashing tutorial]: ../../../tutorial/flashing_firmware/ext_power.md
-[Intel FSP2.0]: ../../../soc/intel/fsp/index.md
+[flashing tutorial]: ../../../../tutorial/flashing_firmware/ext_power.md
+[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
 [AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376

Documentation/northbridge/intel/sandybridge/nri_freq.md

@@ -160,7 +160,7 @@ As you can see, by using DIMMs with different maximum DRAM frequencies, the
 slowest DIMMs' frequency will be selected, to prevent over-clocking it.
 
 The selected frequency gives the PLL multiplier to operate at. In case the PLL
-locks (see Take me to [Hard fuses](#hard-fuses)) the frequency will be used for
+locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for
 all DIMMs. At this point it's not possible to change the multiplier again,
 until the system has been powered off. In case the PLL doesn't lock, the next
 smaller multiplier will be used until a working multiplier will be found.

Documentation/releases/checklist.md

@@ -66,23 +66,13 @@ delayed, the next release will still be 3 months after the last release.
 
 ## Checklist
 
-### ~6 weeks prior to release
+### ~2 weeks prior to release
 - [ ] Announce upcoming release to mailing list, ask people to test and
       to update release notes.
 - [ ] Start marking patches that should to go into the release with a
-      tag "coreboot_release_X.yy".
-
-### ~4 weeks prior to release
-- [ ] Freeze toolchain state. Only relevant fixes are allowed from this point on.
-- [ ] Schedule release meetings.
-
-### ~2 weeks prior to release
-- [ ] Meet with release team.
-- [ ] Send reminder email to mailing list, ask for people to test, and to update the release notes.
-- [ ] Update the topic in the IRC channel with the date of the upcoming release.
+      tag "coreboot_release_X.yy"
 
 ### ~1 week prior to release
-- [ ] Meet with release team.
 - [ ] Send reminder email to mailing list, ask for people to test,
       and to update the release notes.
 - [ ] Update the topic in the IRC channel with the date of the upcoming
@@ -90,22 +80,21 @@ delayed, the next release will still be 3 months after the last release.
 - [ ] If there are any deprecations announced for the following release,
       make sure that a list of currently affected boards and chipsets is
       part of the release notes.
-- [ ] Finalize release notes as much as possible.
-- [ ] Prepare release notes template for following release.
-- [ ] Update `Documentation/releases/index.md.
+- [ ] Finalize release notes as much as possible
+- [ ] Prepare release notes template for following release
+- [ ] Update `Documentation/releases/index.md`
 - [ ] Check which branches need to be released. Any branch with changes
       should get a new release. Announce these branch releases and
       prepare release notes.
 
-### Day before release tag
+### Day before release
 - [ ] Make sure patches with tags for the release are merged.
 - [ ] Announce to IRC that the release will be tomorrow and ask for
       testing.
 - [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
       boards supported by vboot.
 
-### Day of release tag
-- [ ] Meet with release team.
+### Day of release
 - [ ] Review the full documentation about doing the release below.
 - [ ] Select a commit ID to base the release upon.
 - [ ] Test the commit selected for release.
@@ -131,24 +120,11 @@ delayed, the next release will still be 3 months after the last release.
       can be used as release builders.
 
 ### Week following the release
-- [ ] Do the final release notes - Fill in the release date, remove "Upcoming release"
-      and other filler from the current release notes.
-- [ ] ADMIN: Upload release files & toolchain tarballs to the web server.
-- [ ] ADMIN: Upload the final release notes to the web server.
-- [ ] ADMIN: Upload crossgcc sources to the web server.
-- [ ] Create coreboot-sdk and coreboot-jenkins-node docker images based on the release ID
-      and push them to dockerhub. These can be used as release builders.
 - [ ] Update download page to point to files, push to repo.
+- [ ] Write and publish blog post with release final notes. Branch
+      releases notes should be included in the same post.
 - [ ] Remove code that was announced it was going to be removed.
-- [ ] Update AUTHORS file with any new authors.
-- [ ] Update Documentation/releases/boards_supported_on_branches.md.
-
-### 7 days after release tag
-- [ ] Meet with release team.
-- [ ] Write and publish blog post with release final notes. Branch releases notes (if any)
-      should be included in the same post.
-- [ ] Set up for next release.
-
+- [ ] Update `Documentation/releases/boards_supported_on_branches.md`
 
 ### Creating a branch
 - [ ] Branches are named 4.xx_branch to differentiate from the tags.
@@ -254,7 +230,6 @@ commit db508565d2483394b709654c57533e55eebace51 (HEAD, tag: 4.6, origin/master,
 ...
 ````
 
-## Push the signed tag
 When you used the script to generate the release, a signed tag was
 generated in the tree that was downloaded. From the coreboot-X.Y tree,
 just run: `git push origin X.Y`. In case you pushed the wrong tag

Documentation/releases/coreboot-24.02-relnotes.md

@@ -12,7 +12,7 @@ optimization.
 The next release is scheduled for mid-May.
 
 
-## Release number format update
+### Release number format update
 
 The previous release was the last to use the incrementing 4.xx release
 name scheme. For this and future releases, coreboot has switched to a
@@ -22,7 +22,7 @@ of 00 implied. If we need to do a fix or incremental release, we'll
 append the values .01, .02 and so on to the initial release value.
 
 
-## The master branch is being deleted
+### The master branch is being deleted
 
 The coreboot project changed from master to main roughly 6 months ago,
 and has been keeping the two branches in sync since then to ease the
@@ -197,7 +197,8 @@ Significant Known and Open Issues
   the version of verstage used in coreboot 24.02.
 
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+## Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+
 
 ### coreboot-wide or architecture-wide issues
 

Documentation/releases/coreboot-24.05-relnotes.md

@@ -1,76 +1,37 @@
-coreboot 24.05 release
+Upcoming release - coreboot 24.05
 ========================================================================
 
-The coreboot project is pleased to announce the release of coreboot version
-24.05. This update represents three months of hard work and commitment from our
-community. With over 20 new members and contributions from more than a hundred
-fifty other people in coding, reviewing patches, and other areas, this release
-showcases the strength of our collaborative efforts.
+The 24.05 release is scheduled for Mid May, 2024
 
-With this release, coreboot has expanded its support, adding 25 new platforms or
-variants and 2 new processors, further demonstrating our dedication to offering
-flexible and adaptable firmware solutions. From laptops and servers to embedded
-devices, coreboot 24.05 is designed to enhance a variety of hardware platforms
-with its strong features.
 
-We are grateful to all the contributors who have made this release possible.
-Your expertise and collaborative efforts continue to propel the coreboot project
-forward. We value the participation of everyone in the community, from long-time
-developers to those new to the project, and encourage you to explore the new
-opportunities that coreboot 24.05 offers.
+Update this document with changes that should be in the release notes.
 
-Our next release will be 24.08, scheduled for mid-August.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
 
 
 
 Significant or interesting changes
 ----------------------------------
 
-### Mark 64-bit support as stable
+* Add changes that need a full description here
 
-A significant amount of work has gone into fully supporting 64-bit coreboot
-builds. There are still additional pieces that are happening, but with SMM
-holding page tables itself, we can consider SMM support stable and safe enough
-for general use.
-
-
-### security/tpm: support compiling in multiple TPM drivers
-
-Previously, boards could only be built with code supporting TPM 1.x or TPM 2.x
-specifications. This has been updated with code allowing both to be built in
-simultaneously, allowing the system to query the TPM. For systems with
-soldered-down TPMs or firmware TPM solutions, it’s still possible to specify a
-single TPM version so that the code for the other version isn’t included.
-
-
-### arch/arm64: Add EL1/EL2/EL3 support for arm64
-
-Previously, arch/arm64 required coreboot to run on EL3 due to EL3 register
-access. This might be an issue when, for example, one boots into TF-A first and
-drops into EL2 for coreboot afterwards.
-
-This patch aims at making arch/arm64 more versatile by removing the current EL3
-constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3.
-
-The strategy is to add a Kconfig option (ARM64_CURRENT_EL) which allows us to
-specify coreboot's EL upon entry. Based on that, we access the appropriate ELx
-registers. So, for example, when running coreboot on EL1, we would not access
-vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults
-when accessing higher-EL registers.
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
 
 
 
 Additional coreboot changes
 ---------------------------
 
-* util/smmstoretool: support processing ROMs
-* cpu/x86: Link page tables in stage if possible
-* lib/lzmadecode: Allow for 8 byte reads on 64bit to speed up decompression
-* mb/lenovo/*: Set VR12 PSI to fix crash
-* Numerous fixes for clang support
-* Ongoing code cleanup
-* Docs: Replace Recommonmark with MyST Parser. For changes, see the commit
-  message in https://review.coreboot.org/73158
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
 
 
 
@@ -79,29 +40,11 @@ Changes to external resources
 
 ### Toolchain updates
 
-* util/kconfig: Uprev to Linux 6.8's kconfig
-* crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
-* util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
-* crossgcc: Upgrade binutils from 2.41 to 2.42
-* util/crossgcc/buildgcc: Use Intel mirror for ACPICA
-
 
 ### Git submodule pointers
 
-- amd_blobs: Update from commit id 64cdd7c8ef to ae5fc7d277 (1 commits)
-- arm-trusted-firmware: Update from commit id 17bef2248d to 48f1bc9f52 (517
-  commits)
-- cmocka: Update from commit id 8931845c35 to 8be3737209 (32 commits)
-- fsp: Update from commit id 507ef01cce to cc6399e8c7 (14 commits)
-- intel-microcode: Update from commit id ece0d294a2 to 41af345005 (1 commit)
-- vboot: Update from commit id 3d37d2aafe to 09fcd2184f (27 commits)
 
-
-#### External payloads
-
-* payloads/U-Boot: Upgrade from U-Boot v2023.07 to v2024.4
-* payloads/edk2: Add Kconfig options for LAPIC timer & UFS support
-* payloads/Kconfig: Add flat binary as payload option
+### External payloads
 
 
 
@@ -109,155 +52,42 @@ Platform Updates
 ----------------
 
 ### Added mainboards:
-
-* AMD BirmanPlus for Glinda SoC
-* AMD BirmanPlus for Phoenix SoC
-* ASROCK Z97 Extreme6
-* Dell OptiPlex 7020/9020 MT
-* Dell OptiPlex 7020/9020 SFF
-* Framework Azalea (Framework 13 AMD 7040)
-* Google Brox EC ISH
-* Google Bujia
-* Google Glassway
-* Google Greenbayupoc
-* Google Kyogre
-* Google Lotso
-* Google Nova
-* Google Pujjoga
-* Google Riven
-* Google Skitty
-* Google Squirtle
-* Google Sundance
-* Google Tivviks
-* Google Trulo
-* Google Veluza
-* Google Wugtrio
-* Google Yavista
-* HP Pro 3500 Series
-* Lenovo ThinkCentre M700 / M900 Tiny
-* Lenovo ThinkCentre M710s
-* Raptor Computing Systems Talos II
-* SiFive HiFive Unmatched
+* To be filled in immediately before the release by the release team
 
 
 ### Removed Mainboards
-
-* Intel Alderlake-M RVP
-* Intel Alderlake-M RVP with Chrome EC
+* To be filled in immediately before the release by the release team
 
 
 ### Updated SoCs
-
-* Added src/soc/ibm/power9
-* Added src/soc/intel/xeon_sp/gnr
-* Added src/soc/sifive/fu740
+* To be filled in immediately before the release by the release team
 
 
 
-Statistics from the 24.02 to the 24.05 release
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 4.22 to the 24.02 release
 --------------------------------------------
+* To be filled in immediately before the release by the release team
 
-* Total Commits: 739
-* Average Commits per day: 8.64
-* Total lines added: 304721
-* Average lines added per commit: 412.34
-* Number of patches adding more than 100 lines: 60
-* Average lines added per small commit: 37.74
-* Total lines removed: 16195
-* Average lines removed per commit: 21.91
-* Total difference between added and removed: 288526
-* Total authors: 131
-* New authors: 23
 
 
 Significant Known and Open Issues
 ---------------------------------
 
-## coreboot-wide or architecture-wide issues
+Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+* To be filled in immediately before the release by the release team
 
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 522 | 'region_overlap()' issues due to an integer overflow.           |
-+-----+-----------------------------------------------------------------+
-| 519 | make gconfig - could not find glade file                        |
-+-----+-----------------------------------------------------------------+
-| 518 | make xconfig - g++: fatal error: no input files                 |
-+-----+-----------------------------------------------------------------+
-```
-
-
-## Payload-specific issues
-
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 496 | Missing malloc check in libpayload                              |
-+-----+-----------------------------------------------------------------+
-| 484 | No USB keyboard support with secondary payloads                 |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-```
-
-
-## Platform-specific issues
-
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx    |
-+-----+-----------------------------------------------------------------+
-| 517 | lenovo x230 boot stuck with connected external monitor          |
-+-----+-----------------------------------------------------------------+
-| 509 | SD Card hotplug not working on Apollo Lake                      |
-+-----+-----------------------------------------------------------------+
-| 507 | Windows GPU driver fails on Google guybrush & skyrim boards     |
-+-----+-----------------------------------------------------------------+
-| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
-+-----+-----------------------------------------------------------------+
-| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
-+-----+-----------------------------------------------------------------+
-| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-```
 
 
 coreboot Links and Contact Information
 --------------------------------------
 
-* Main Website: https://www.coreboot.org
+* Main Web site: https://www.coreboot.org
 * Downloads: https://coreboot.org/downloads.html
 * Source control: https://review.coreboot.org
 * Documentation: https://doc.coreboot.org

Documentation/releases/coreboot-24.08-relnotes.md

@@ -1,413 +0,0 @@
-Upcoming release - coreboot 24.08
-========================================================================
-
-We are pleased to announce the release of coreboot 24.08, another significant
-milestone in our ongoing commitment to delivering open-source firmware
-solutions. This release includes over 900 commits, contributed by more than 130
-dedicated individuals from our global community. The updates in 24.08 bring
-various enhancements, optimizations, and new features that further improve the
-reliability and performance of coreboot across supported platforms.
-
-We extend our sincere thanks to the patch authors, reviewers, and everyone
-involved in the coreboot community for their hard work and dedication. Your
-contributions continue to advance and refine coreboot with each release. As
-always, thank you for your support and collaboration in driving the future of
-open-source firmware. The next coreboot release, 24.11 is planned for mid
-November.
-
-
-
-Significant or interesting changes
-----------------------------------
-
-### Introduce region_create() functions
-
-We introduce two new functions to create region objects. They allow us to check
-for integer overflows (`region_create_untrusted()`) or assert their absence
-(`region_create()`).
-
-This fixes potential overflows in `region_overlap()` checks in SMI handlers, where
-we would wrongfully report MMIO as *not* overlapping SMRAM.
-
-Also, two cases of `strtol()` in `parse_region()` (cbfstool), where the results were
-implicitly converted to `size_t`, are replaced with the unsigned `strtoul()`.
-
-FIT payload support is left out, as it doesn't use the region API (only the
-struct).
-
-Ticket: <https://ticket.coreboot.org/issues/522> \
-Review: <https://review.coreboot.org/79905>
-
-
-### lib/device_tree: Add some FDT helper functions
-
-This adds some helper functions for FDT (Flattened Device Tree) , since more and
-more mainboards seem to need FDT nowadays. For example our QEMU boards need it
-in order to know how much RAM is available. Also all RISC-V boards in our tree
-need FDT.
-
-This also adds some tests in order to test said functions.
-
-Review: <https://review.coreboot.org/c/coreboot/+/81081>
-
-
-### device_tree: Add function to get top of memory from a FDT blob
-
-coreboot needs to figure out top of memory to place CBMEM data. On some non-x86
-QEMU virtual machines, this is achieved by probing the RAM space to find where
-the VM starts discarding data since it's not backed by actual RAM. This behavior
-seems to have changed on the QEMU side since then, VMs using the "virt" model
-have started raising exceptions/errors instead of silently discarding data
-(likely [1] for example) which has previously broken coreboot on these emulation
-boards.
-
-The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt" models
-and had this issue, which was mostly fixed by using exception handlers in the
-RAM detection process [2][3]. But on 32-bit RISC-V we fail to initialize CBMEM
-if we have 2048 MiB or more of RAM, and on 64-bit RISC-V we had to limit probing
-to 16383 MiB because it can run into MMIO regions otherwise.
-
-The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM which
-doesn't appear to suffer from this issue. Still, the issue can be observed on
-the ARMv7 "virt" model via a port based on qemu-aarch64.
-
-QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the device
-tree blob it provides for device information (incl. RAM size). Implement
-functions that parse the device tree blob to find described memory regions and
-calculate the top of memory in order to use it in mainboard code as an
-alternative to probing RAM space. ARM64 code initializes CBMEM in romstage where
-malloc isn't available, so take care to do parsing without unflattening the blob
-and make the code available in romstage as well.
-
-[1] <https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.maydell@linaro.org/T/#u> \
-[2] <https://review.coreboot.org/c/coreboot/+/34774> \
-[3] <https://review.coreboot.org/c/coreboot/+/36486> \
-[4] <https://qemu-project.gitlab.io/qemu/system/arm/virt.html> \
-[5] <https://qemu-project.gitlab.io/qemu/system/riscv/virt.html>
-
-Review: <https://review.coreboot.org/c/coreboot/+/80322>
-
-
-### drivers/wifi: Support Bluetooth Regulator Domain Settings
-
-The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides ability
-to utilize increased device Transmit power capability for Bluetooth applications
-in coordination with Wi-Fi adhering to product SAR (Specific Absorption Rate)
-limit when Bluetooth and Wi-Fi run together.
-
-This commit introduces a `bluetooth_companion' field to the generic Wi-Fi
-drivers chip data. This field can be set in the board design device tree to
-supply the bluetooth device for which the BRDS function must be created.
-
-The implementation follows document 559910 Intel Connectivity Platforms BIOS
-Guideline revision 8.3 specification.
-
-Review: <https://review.coreboot.org/c/coreboot/+/83200>
-
-
-### acpigen_ps2_keybd: Support Do Not Disturb & Accessibility Keys
-
-These commits add support for a Do Not Disturb key and an Accessibility key.
-
-HUTRR94 added support for a new usage titled "System Do Not Disturb" which
-toggles a system-wide Do Not Disturb setting.
-
-HUTRR116 added support for a new usage titled "System Accessibility Binding"
-which toggles a system-wide bound accessibility UI or command.
-
-HUTRR94: <https://www.usb.org/sites/default/files/hutrr94_-_system_do_not_disturb.pdf> \
-HUTRR116: <https://www.usb.org/sites/default/files/hutrr116-systemaccessbilitybinding_2.pdf>
-
-Review: <https://review.coreboot.org/c/coreboot/+/82997> \
-Review: <https://review.coreboot.org/c/coreboot/+/82996>
-
-
-### superio/ite/common: Add common driver for GPIO and LED configuration
-
-Add a generic driver to configure GPIOs and LEDs on common ITE SuperIOs. The
-driver supports most ITE SuperIOs, except Embedded Controllers. The driver
-allows configuring every GPIO property with pin granularity.
-
-Verified against datasheets of all ITE SIOs currently supported by coreboot,
-except IT8721F (assumed to be the same as IT8720F), IT8623E and IT8629E.
-
-Review: <https://review.coreboot.org/c/coreboot/+/83355>
-
-
-### util/cbfstool: Fix linux_trampoline.c generation
-
-linux_trampoline.c generation is broken with latest crossgcc-i386 toolchain. Fix
-the issue to enable the building.
-
-```
-../cbfstool/linux_trampoline.S: Assembler messages:
-../cbfstool/linux_trampoline.S:100: Error: no instruction mnemonic
-	suffix given and no register operands; can't size instruction
-<builtin>: recipe for target '../cbfstool/linux_trampoline.o' failed
-```
-
-Review: <https://review.coreboot.org/c/coreboot/+/82704>
-
-
-### Add LeanEFI payload
-
-This adds another external payload to coreboot. The payload has been heavily
-based on u-boots UEFI implementation.
-
-The LeanEFI payload is basically a translator from coreboot to UEFI. It takes
-the coreboot tables and transforms them into UEFI interfaces. Although it can
-potentially load any efi application that can handle the minimized interface
-that LeanEFI provides, it has only been tested with LinuxBoot (v6.3.5) as a
-payload. It has been optimized to support only those interfaces that Linux
-requires to start.
-
-Among other LeanEFI does not support:
-- efi capsule update (also efi system resource table)
-- efi variables
-- efi text input protocol (it can only output)
-- most boot services. mostly memory services are left (e.g. alloc/free)
-- all runtime services (although there is still a very small runtime
-  footprint that is planned to be removed in the near future)
-- TCG2/TPM (although that is mostly because of laziness)
-The README.md currently provides more details on why.
-
-The payload currently only supports arm64 and has only been tested on
-emulation/simulator targets. The original motivation was to get ACPI on arm64
-published to the OS without using EDK2. It is however also possible to supply
-the LeanEFI with a FDT that is published to the OS. At that point one would
-however probably use coreboot only instead of this shim layer on top. It would
-be way nicer to have Linux support something other than UEFI to propagate the
-ACPI tables, but it requires getting the Linux maintainer/community on board. So
-for now this shim layer circumvents that.
-
-LBBR Test:
-1. dump FDT from QEMU like mentioned in aarch64 coreboot doc
-2. compile u-root however you like (aarch64)
-3. compile Linux (embed u-root initramfs via Kconfig)
-4. copy Linux kernel to payloads/leanefi/Image
-5. copy following coreboot defconfig to configs/defconfig:
-```
-CONFIG_BOARD_EMULATION_QEMU_AARCH64=y
-CONFIG_PAYLOAD_NONE=n
-CONFIG_PAYLOAD_LEANEFI=y
-CONFIG_LEANEFI_PAYLOAD=y
-CONFIG_LEANEFI_PAYLOAD_PATH="[path-to-linux]/arch/arm64/boot/Image"
-CONFIG_LEANEFI_FDT=y
-CONFIG_LEANEFI_FDT_PATH="[path-to-dumped-DTB]"
-```
-6. compile coreboot \
-`make defconfig` \
-`make -j$(nproc)`
-7. run qemu like mentioned in coreboot doc (no FIT)
-8. say hello to u-root and optionally kexec into the next kernel
-
-Review: <https://review.coreboot.org/c/coreboot/+/78913>
-
-
-
-Additional coreboot changes
----------------------------
-
-* Dropped ChromeEC as a submodule.
-* Numerous updates to autoport tool, including Haswell support.
-* Upgrade to Wuffs 0.4.0-alpha.8
-* Add x86_64 (64-bit) support to LibPayload
-* Add hda-decoder utility that dumps decoded HDA default configuration registers
-* Add SBMIOS tables for arm64 platforms
-* cpu/x86/lapic: Always have LAPIC enabled
-* arch/arm64: Support calling a trusted monitor
-* drivers/wifi: Support Wi-Fi 7 11be Enablement
-* drivers/wifi: Support Radio Frequency Interference Mitigation
-
-
-
-Changes to external resources
------------------------------
-
-### Toolchain updates
-
-* Upgrade CMake from 3.28.3 to 3.29.3
-* Upgrade nasm from 2.16.01 to 2.16.03
-* Upgrade LLVM from 17.0.6 to 18.1.6
-* Upgrade GCC from 13.2 to 14.1.0
-
-
-### Git submodule pointers
-
-* /3rdparty/amd_blobs: Update from commit ae5fc7d277 to 26c572974b (2 commits)
-* /3rdparty/arm-trusted-firmware: Update from commit 48f1bc9f52 to c5b8de86c8 (430 commits)
-* /3rdparty/fsp: Update from commit cc6399e8c7 to 800c85770b (23 commits)
-* /3rdparty/intel-microcode: Update from commit 41af345005 to 5278dfcf98 (2 commits)
-* /3rdparty/libgfxinit: Update from commit a4be8a21b0 to 17cfc92f40 (5 commits)
-* /3rdparty/vboot: Update from commit 09fcd2184f to f1f70f46dc (69 commits)
-
-
-Platform Updates
-----------------
-
-### New mainboards:
-
-* Acer Q45T-AM
-* AOOSTAR WTR R1
-* ASROCK Fatal1ty Z87 Professional
-* ASROCK Z87E-ITX
-* ASROCK Z87M OC Formula
-* ASROCK Z97E-ITX/ac
-* CWWK CW-ADL-4L-V1.0
-* Dell Inc. Latitude E6430
-* Dell Inc. Latitude E7240
-* Dell Inc. XPS 8300
-* Emulation QEMU sbsa
-* GIGABYTE GA-H61M-S2P-R3
-* Google Awasuki
-* Google Brox TI PDC
-* Google Domika
-* Google Fatcat
-* Google Jubilant
-* Google Orisa
-* Google Rauru
-* Google Rex 64
-* Google Teliks
-* Google Tereid
-* HP EliteBook 8560w
-* Intel Avenue City CRB
-* Intel Beechnut City CRB
-* Protectli VP6630/VP6650/VP6670
-* Star Labs Star Labs Lite Mk V (N200)
-* System76 addw4
-* System76 darp10
-* System76 darp10-b
-* System76 oryp12
-
-
-### Updated SoCs & socket definitions
-
-* Added src/cpu/intel/socket_LGA1700
-* Added src/cpu/intel/socket_LGA3647_1
-* Added src/cpu/intel/socket_LGA4189
-* Added src/cpu/intel/socket_LGA4677
-* Added src/soc/intel/pantherlake
-* Added src/soc/mediatek/mt8196
-
-
-
-Statistics from the 24.05 to the 24.08 release
-----------------------------------------------
-
-* Total Commits: 883
-* Average Commits per day: 8.78
-* Total lines added: 105457
-* Average lines added per commit: 119.43
-* Number of patches adding more than 100 lines: 98
-* Average lines added per small commit: 37.67
-* Total lines removed: 18689
-* Average lines removed per commit: 21.17
-* Total difference between added and removed: 86768
-* Total authors: 136
-* New authors: 33
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-### coreboot-wide or architecture-wide issues
-
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 519 | make gconfig - could not find glade file                        |
-+-----+-----------------------------------------------------------------+
-| 518 | make xconfig - g++: fatal error: no input files                 |
-+-----+-----------------------------------------------------------------+
-```
-
-
-### Payload-specific issues
-
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 552 |  X201 not booting with edk2 payload                             |
-+-----+-----------------------------------------------------------------+
-| 549 | SeaBIOS Windows 10/11 BSOD "ACPI BIOS ERROR" (Thinkpad W530)    |
-+-----+-----------------------------------------------------------------+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 496 | Missing malloc check in libpayload                              |
-+-----+-----------------------------------------------------------------+
-| 484 | No USB keyboard support with secondary payloads                 |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-```
-
-
-### Platform-specific issues
-
-```{eval-rst}
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 548 | Lenovo X201 Fails To Recognize Upgraded WiFi Card               |
-+-----+-----------------------------------------------------------------+
-| 538 | x230: Dock Causes Internal Display to "Permanently" Malfunction |
-+-----+-----------------------------------------------------------------+
-| 535 | T420: Power light stays off after reboot                        |
-+-----+-----------------------------------------------------------------+
-| 528 | Building qemu-i440fx with CONFIG_CBFS_VERIFICATION fails        |
-+-----+-----------------------------------------------------------------+
-| 524 | X2APIC Options cause Linux to crash on emulation/qemu-i440fx    |
-+-----+-----------------------------------------------------------------+
-| 517 | lenovo x230 boot stuck with connected external monitor          |
-+-----+-----------------------------------------------------------------+
-| 509 | SD Card hotplug not working on Apollo Lake                      |
-+-----+-----------------------------------------------------------------+
-| 507 | Windows GPU driver fails on Google guybrush & skyrim boards     |
-+-----+-----------------------------------------------------------------+
-| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
-+-----+-----------------------------------------------------------------+
-| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
-+-----+-----------------------------------------------------------------+
-| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-```
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Web site: <https://www.coreboot.org>
-* Downloads: <https://coreboot.org/downloads.html>
-* Source control: <https://review.coreboot.org>
-* Documentation: <https://doc.coreboot.org>
-* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
-* Donations: <https://coreboot.org/donate.html>

Documentation/releases/coreboot-24.11-relnotes.md

@@ -1,95 +0,0 @@
-Upcoming release - coreboot 24.11
-========================================================================
-
-The 24.11 release is scheduled for Mid November, 2024
-
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-
-
-Significant or interesting changes
-----------------------------------
-
-* Add changes that need a full description here
-
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
-
-
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-
-
-Changes to external resources
------------------------------
-
-### Toolchain updates
-
-
-### Git submodule pointers
-
-
-### External payloads
-
-
-
-Platform Updates
-----------------
-
-### Added mainboards:
-* To be filled in immediately before the release by the release team
-
-
-### Removed Mainboards
-* To be filled in immediately before the release by the release team
-
-
-### Updated SoCs
-* To be filled in immediately before the release by the release team
-
-
-
-Plans to move platform support to a branch
-------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Statistics from the 24.08 to the 24.11 release
---------------------------------------------
-* To be filled in immediately before the release by the release team
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-* To be filled in immediately before the release by the release team
-
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Web site: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html

Documentation/releases/coreboot-4.13-relnotes.md

@@ -214,7 +214,7 @@ Deprecations
 
 In order to minimize the usage of PCI bus mastering, the options we introduced in
 this release will be dropped in a future release again. For more details, please
-see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering).
+see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot).
 
 ### Resource allocator v3
 

Documentation/releases/coreboot-4.21-relnotes.md

@@ -13,7 +13,7 @@ about the coreboot project. There have been a number of new companies
 starting to use coreboot recently, and we appreciate all of the
 contributions and support.
 
-## Upcoming switch from master branch to main branch
+### Upcoming switch from master branch to main branch
 
 Historically, the initial branch that was created in a new git
 repository was named ‘master’. In line with many other projects,

Documentation/releases/coreboot-4.22-relnotes.md

@@ -11,7 +11,7 @@ releases, this one reflects a commitment to open source innovation,
 security enhancements, and expanding hardware support.
 
 
-## 4.22.01 release
+### 4.22.01 release
 
 The week between tagging a release and announcing it publicly is used
 to test the tagged version and make sure everything is working as we
@@ -22,7 +22,7 @@ For the 4.22 release cycle we found an uninitialized variable error on
 the sandybridge/ivybridge platforms and rolled that into the 4.22.01
 release package.
 
-## coreboot version naming update
+### coreboot version naming update
 
 This release is the last release to use the incrementing 4.xx release
 name scheme. For future releases, coreboot is switching to a
@@ -33,7 +33,7 @@ the 24.02 release, we'll append the values .01, .02 and so on to the
 initial release value.
 
 
-## coreboot default branch update
+### coreboot default branch update
 
 Immediately after the 4.21 release, the coreboot project changed the
 default git branch from 'master' to 'main'. For the first couple of

Documentation/releases/index.md

@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-24.11 - November 2024 <coreboot-24.11-relnotes.md>
+24.05 - May 2024 <coreboot-24.05-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,8 +22,6 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
-24.08  - August 2024 <coreboot-24.08-relnotes.md>
-24.05  - May 2024 <coreboot-24.05-relnotes.md>
 24.02  - February 2024 <coreboot-24.02-relnotes.md>
 4.22   - November 2023 <coreboot-4.22-relnotes.md>
 4.21   - August 2023 <coreboot-4.21-relnotes.md>

Documentation/security/vboot/list_vboot.md

@@ -4,8 +4,6 @@
 - Birman for Phoenix SoC using FSP
 - Birman for Phoenix SoC using openSIL
 - Birman for Glinda SoC
-- BirmanPlus for Phoenix SoC
-- BirmanPlus for Glinda SoC
 - Chausie
 - Majolica
 - Mayan for Phoenix SoC
@@ -37,11 +35,6 @@
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
 - Brox
-- Brox EC ISH
-- Brox TI PDC
-- Greenbayupoc
-- Jubilant
-- Lotso
 - Agah
 - Anahera
 - Anahera4ES
@@ -55,13 +48,11 @@
 - Constitution
 - Crota
 - Dochi
-- Domika
 - Felwinter
 - Gaelin
 - Gimble
 - Gimble4ES
 - Gladios
-- Glassway
 - Gothrax
 - Hades
 - Kano
@@ -83,16 +74,11 @@
 - Quandiso
 - Redrix
 - Redrix4ES
-- Riven
 - Skolas
 - Skolas4ES
 - Taeko
 - Taeko4ES
 - Taniks
-- Teliks
-- Tereid
-- Tivviks
-- Trulo
 - Uldren
 - Vell
 - Volmar
@@ -101,30 +87,19 @@
 - Yavilla
 - Zydron
 - Xol
-- Nova
-- Bujia
-- Yavista
-- Sundance
-- Pujjoga
-- Orisa
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
 - Tomato
 - Kingler
-- Kyogre
-- Ponyta
-- Squirtle
 - Steelix
 - Voltorb
-- Chinchou
+- Ponyta
 - Krabby
-- Magikarp
-- Skitty
 - Tentacruel
-- Veluza
+- Magikarp
+- Chinchou
 - Starmie
-- Wugtrio
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -138,7 +113,6 @@
 - Wizpig
 - Drallion
 - Eve (Google Pixelbook)
-- Fatcat
 - Fizz
 - Karma
 - Endeavour
@@ -242,7 +216,6 @@
 - Puff
 - Scout
 - Wyvern (CTL Chromebox CBx2)
-- Rauru
 - Reef/Electro (Acer Chromebook Spin 11 R751T)
 - Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
@@ -258,7 +231,6 @@
 - Rex EC ISH
 - Rex4ES
 - Rex4ES EC ISH
-- Rex 64
 - Screebo
 - Screebo4ES
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
@@ -326,7 +298,6 @@
 - Woomax (ASUS Chromebook Flip CM5)
 
 ## HP
-- Compaq Elite 8300 USDT
 - Z220 CMT Workstation
 - Z220 SFF Workstation
 
@@ -334,6 +305,8 @@
 - Alderlake-P RVP
 - Alderlake-P RVP with Chrome EC
 - Alderlake-P RVP with Microchip EC
+- Alderlake-M RVP
+- Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
 - Raptorlake silicon with Alderlake-P RVP
@@ -392,7 +365,6 @@
 - ThinkPad X230
 - ThinkPad X230t
 - ThinkPad X230s
-- ThinkPad X230 eDP Mod (2K/FHD)
 - ThinkPad X60 / X60s / X60t
 
 ## MSI
@@ -405,8 +377,8 @@
 - Elgon (GBCv2)
 
 ## Protectli
-- VP6630/VP6650/VP6670
-- VP4630/VP4650/VP4670
+- VP4630/VP4650
+- VP4670
 - VP2420
 
 ## SAMSUNG
@@ -430,7 +402,6 @@
 - Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
 - Star Labs StarBook Mk VI (i3-1220P and i7-1260P)
 - Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
-- Star Labs Lite Mk V (N200)
 
 ## Supermicro
 - X11SSH-TF

Documentation/soc/intel/cse_fw_update/cse_fw_update.md

@@ -1,4 +1,4 @@
-# CSE FW update mechanism for devices in field
+CSE FW update mechanism for devices in field
 
 ## Introduction
 

Documentation/superio/nuvoton/npcd378.md

@@ -78,7 +78,7 @@ Looks like a WDT.
 ### LDN8
 
 Custom HWM space. It exposes 256 byte of IO config space.
-See [HWM](#hwm) for more details.
+See [HWM](#HWM) for more details.
 
 ## HWM
 

Documentation/tutorial/part1.md

@@ -30,7 +30,7 @@ Download, configure, and build coreboot
 
 Debian based distros:
 `sudo apt-get install -y bison build-essential curl flex git gnat
-libncurses-dev libssl-dev zlib1g-dev pkgconf`
+libncurses5-dev libssl-dev m4 zlib1g-dev pkg-config`
 
 Arch based distros:
 `sudo pacman -S base-devel curl git gcc-ada ncurses zlib`
@@ -86,7 +86,7 @@ make -C payloads/coreinfo
 
 ### Step 5 - Configure the build
 
-#### Configure your mainboard
+##### Configure your mainboard
 
 ```Bash
 make menuconfig
@@ -104,7 +104,7 @@ select < Exit >
 These should be the default selections, so if anything else was set, run
 `make distclean` to remove your old config file and start over.
 
-#### Optionally use your system toolchain (Again, not recommended)
+##### Optionally use your system toolchain (Again, not recommended)
 
 ```Text
 select 'General Setup' menu
@@ -112,7 +112,7 @@ select 'Allow building with any toolchain'
 select < Exit >
 ```
 
-#### Select the payload
+##### Select the payload
 
 ```Text
 select 'Payload' menu
@@ -125,7 +125,7 @@ select < Exit >
 select < Yes >
 ```
 
-#### Check your configuration (optional step):
+##### Check your configuration (optional step):
 
 ```Bash
 make savedefconfig
@@ -149,7 +149,7 @@ CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
 
 Note that this may differ depending on the revision of the coreboot
 source you are building from and should not be taken as the required
-contents of defconfig.
+contents of defconfig. 
 
 ### Step 6 - Build coreboot
 
@@ -202,11 +202,11 @@ of the installed packages:
 
 * `build-essential` or `base-devel` are the basic tools for building software.
 * `git` is needed to download coreboot from the coreboot git repository.
-* `libncurses-dev` or `ncurses` is needed to build the menu for 'make menuconfig'
+* `libncurses5-dev` or `ncurses` is needed to build the menu for 'make menuconfig'
 * `m4, bison, curl, flex, zlib1g-dev, gcc, gnat` and `g++` or `clang`
 are needed to build the coreboot toolchain. `gcc` and `gnat` have to be
 of the same version.
-* `libssl-dev, pkgconf` are needed to build coreboot image (Step 6).
+* `libssl-dev, pkg-config` are needed to build coreboot image (Step 6).
 In particular, `libcrypto` provided by `libssl-dev` package.
 
 If you started with a different distribution or package management

Documentation/util/abuild/index.md

@@ -14,7 +14,7 @@ to make sure your patch compiles cleanly for all.
 Note that abuild is a tool to do a simple build test, and binaries it
 produces may well not boot if flashed to a system.
 
-## Basic usage
+### Basic usage
 
 abuild needs to be run from the coreboot directory. If you cd into the
 coreboot/util/abuild directory and try to run it from there, it will
@@ -30,7 +30,7 @@ example, to build the Lenovo X230 target, run:
 $ util/abuild/abuild -t lenovo/x230
 ```
 
-## Where builds and logs are stored
+### Where builds and logs are stored
 
 The resulting images and logs are stored in directory coreboot-builds/
 under your current directory. This can be overridden with --outdir:
@@ -53,7 +53,7 @@ coreboot-builds/passing_boards and coreboot-builds/failing_boards.
 **These logs are overwritten with each abuild run.** Save them elsewhere
 if you feel a need to reference the results later.
 
-## Payloads
+### Payloads
 
 You can also specify a payload directory with -p:
 
@@ -81,7 +81,7 @@ You can also tell abuild not to use a payload:
 util/abuild/abuild -t lenovo/x230 -p none
 ```
 
-## Build non-default configurations
+### Build non-default configurations
 
 Sometimes you do need to build test a custom, non-default configuration.
 This can be accomplished by placing a config file in configs/.
@@ -142,7 +142,7 @@ a file named `myconfig` with this line:
 and run `abuild -K myconfig` to build everything with a silent postcar
 stage.
 
-## Selectively build certain targets only (also config file naming caveats)
+### Selectively build certain targets only (also config file naming caveats)
 
 The P8Z77-M PRO example above would fail for P8Z77-M, because the
 config file name is ambiguous. `abuild` would pick up this config when
@@ -166,7 +166,7 @@ util/abuild/abuild --skip_unset USE_NATIVE_RAMINIT
 This example skips building configs not using (Sandy/Ivy Bridge) native
 RAM init.
 
-## Additional Examples
+### Additional Examples
 
 Many boards have multiple variants. You can build for a specific
 variant of a board:
@@ -203,7 +203,7 @@ Of course, the real power of abuild is in testing multiple boards.
 util/abuild/abuild -B -y -c 8 -p none
 ```
 
-## Full options list
+### Full options list
 
 ```text
 coreboot autobuild v0.11.01 (Feb 3, 2023)

Documentation/util/intelp2m/index.md

@@ -11,7 +11,7 @@ make
 ./intelp2m -file /path/to/inteltool.log
 ```
 
-## Platforms
+### Platforms
 
 It is possible to use templates for parsing inteltool.log files.
 To specify such a pattern, use the option `-t <template number>`.
@@ -51,13 +51,13 @@ platform type is set using the -p option (Sunrise by default):
 ./intelp2m -p <platform> -file path/to/inteltool.log
 ```
 
-## Packages
+### Packages
 
 ![][pckgs]
 
 [pckgs]: gopackages.png
 
-## Bit fields in macros
+### Bit fields in macros
 
 Use the `-fld=cb` option to only generate a sequence of bit fields in
 a new macro:
@@ -71,7 +71,7 @@ _PAD_CFG_STRUCT(GPIO_37, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_TRIG(OFF), \
     PAD_PULL(DN_20K)), /* LPSS_UART0_TXD */
 ```
 
-## Raw DW0, DW1 register value
+### Raw DW0, DW1 register value
 
 To generate the gpio.c with raw PAD_CFG_DW0 and PAD_CFG_DW1 register
 values you need to use the -fld=raw option:
@@ -96,7 +96,7 @@ _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
 _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
 ```
 
-## Macro Check
+### Macro Check
 
 After generating the macro, the utility checks all used
 fields of the configuration registers. If some field has been
@@ -115,7 +115,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
 PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
 ```
 
-## Information level
+### Information level
 
 The utility can generate additional information about the bit
 fields of the DW0 and DW1 configuration registers. Using the
@@ -158,7 +158,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, \
     DISPUPD),
 ```
 
-## Ignoring Fields
+### Ignoring Fields
 
 Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields
 from it that are not in the corresponding PAD_CFG_*() macro:
@@ -177,7 +177,7 @@ _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), \
     PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
 ```
 
-## FSP-style macro
+### FSP-style macro
 
 The utility allows one to generate macros that include fsp/edk2-platform
 style bitfields:
@@ -205,6 +205,6 @@ style bitfields:
   GpioPadConfigLock },
 ```
 
-## Supported Chipsets
+### Supported Chipsets
 
   Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs

MAINTAINERS

@@ -263,12 +263,11 @@ DELL MAINBOARDS
 S:	Orphan
 F:	src/mainboard/dell/
 
-DELL LATITUDE MAINBOARDS
+DELL E6400 MAINBOARD
 M:	Nicholas Chin <nic.c3.14@gmail.com>
 S:	Maintained
 F:	src/mainboard/dell/e6400/
-F:	src/mainboard/dell/snb_ivb_latitude/
-F:	src/mainboard/dell/e7240/
+
 
 
 EMULATION MAINBOARDS
@@ -337,16 +336,9 @@ M:	Nick Vaccaro <nvaccaro@chromium.org>
 M:	Eric Lai <ericllai@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
 M:	Dinesh Gehlot <digehlot@google.com>
-M:	Rishika Raj <rishikaraj@google.com>
-M:	Jayvik Desai <jayvik@google.com>
 S:	Maintained
 F:	src/mainboard/google/brya/
 
-GOOGLE FATCAT MAINBOARDS
-M:	Subrata Banik <subratabanik@google.com>
-M:	Pranava Y N <pranavayn@google.com>
-F:	src/mainboard/google/fatcat/
-
 GOOGLE HATCH MAINBOARDS
 M:	Subrata Banik <subratabanik@google.com>
 M:	Nick Vaccaro <nvaccaro@chromium.org>
@@ -604,8 +596,7 @@ F:	src/mainboard/siemens/mc_ehl/
 
 
 SIFIVE MAINBOARDS
-M:	Maximilian Brune <maximilian.brune@9elements.com>
-S:	Maintained
+S:	Orphan
 F:	src/mainboard/sifive/
 
 
@@ -666,7 +657,6 @@ F:	src/mainboard/emulation/qemu-power8/
 
 RISC-V ARCHITECTURE
 M:	Ronald Minnich <rminnich@gmail.com>
-M:	Maximilian Brune <maximilian.brune@9elements.com>
 R:	Philipp Hug <philipp@hug.cx>
 S:	Maintained
 F:	src/arch/riscv/
@@ -789,11 +779,6 @@ M:	Ronak Kanabar <ronak.kanabar@intel.com>
 S:	Maintained
 F:	src/drivers/intel/fsp2_0/
 
-INTEL DPTF
-M:	Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
-S:	Maintained
-F:	src/drivers/intel/dptf/
-
 ################################################################################
 # Systems on a Chip
 ################################################################################
@@ -866,8 +851,6 @@ M:	Subrata Banik <subratabanik@google.com>
 M:	Nick Vaccaro <nvaccaro@chromium.org>
 M:	Kapil Porwal <kapilporwal@google.com>
 M:	Dinesh Gehlot <digehlot@google.com>
-M:	Rishika Raj <rishikaraj@google.com>
-M:	Jayvik Desai <jayvik@google.com>
 S:	Maintained
 F:	src/soc/intel/alderlake/
 
@@ -910,13 +893,6 @@ M:	Dinesh Gehlot <digehlot@google.com>
 S:	Maintained
 F:	src/soc/intel/meteorlake/
 
-INTEL PANTHERLAKE SOC
-M:	Subrata Banik <subratabanik@google.com>
-M:	Kapil Porwal <kapilporwal@google.com>
-M:	Pranava Y N <pranavayn@google.com>
-S:	Maintained
-F:	src/soc/intel/pantherlake/
-
 INTEL TIGERLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
 M:	Nick Vaccaro <nvaccaro@chromium.org>

Makefile

@@ -94,15 +94,10 @@ help_coreboot help::
 	@echo  '  sphinx                - Build sphinx documentation for coreboot'
 	@echo  '  sphinx-lint           - Build sphinx documentation for coreboot with warnings as errors'
 	@echo  '  filelist              - Show files used in current build'
-	@echo  '  printall              - Print makefile info for debugging'
-	@echo  '  gitconfig             - Set up git to submit patches to coreboot'
-	@echo  '  ctags / ctags-project - Make ctags file for all of coreboot or current board'
-	@echo  '  cscope / cscope-project - Make cscope.out file for coreboot or current board'
-	@echo
-	@echo  '*** site-local related targets ***'
-	@echo  '  symlink               - Create symbolic links from site-local into coreboot tree'
-	@echo  '  clean-symlink         - Remove symbolic links created by "make symlink"'
-	@echo  '  cleanall-symlink      - Remove all symbolic links in the coreboot tree'
+	@echo  '  printall              - print makefile info for debugging'
+	@echo  '  gitconfig             - set up git to submit patches to coreboot'
+	@echo  '  ctags / ctags-project - make ctags file for all of coreboot or current board'
+	@echo  '  cscope / cscope-project - make cscope.out file for coreboot or current board'
 	@echo
 
 # This include must come _before_ the pattern rules below!
@@ -222,7 +217,8 @@ endif
 
 # The primary target needs to be here before we include the
 # other files
-real-all: site-local-target real-target
+
+real-all: real-target
 
 # must come rather early
 .SECONDARY:
@@ -491,77 +487,27 @@ sphinx:
 sphinx-lint:
 	$(MAKE) SPHINXOPTS=-W -C Documentation sphinx
 
-# Look at all of the files in the SYMLINK_LIST and create the symbolic links
-# into the coreboot tree. Each symlink.txt file in site-local should be in the
-# directory linked from and have a single line with the path to the location to
-# link to. The path must be relative to the top of the coreboot directory.
 symlink:
-	if [ -z "$(SYMLINK_LIST)" ]; then \
-		echo "No site-local symbolic links to create."; \
-		exit 0; \
-	fi; \
-	echo "Creating symbolic links.."; \
+	@echo "Creating Symbolic Links.."; \
 	for link in $(SYMLINK_LIST); do \
-		LINKTO="$(top)/$$(head -n 1 "$${link}")"; \
-		LINKFROM=$$(dirname "$$(realpath "$${link}")"); \
-		if [ -L "$${LINKTO}" ]; then \
-			echo "  $${LINKTO} exists - skipping"; \
+		SYMLINK=`cat $$link`; \
+		REALPATH=`realpath $$link`; \
+		if [ -L "$$SYMLINK" ]; then \
 			continue; \
-		fi; \
-		LINKTO="$$(realpath -m "$${LINKTO}")" 2>/dev/null; \
-		if [ "$${LINKTO}" = "$$(echo "$${LINKTO}" | sed "s|^$(top)||" )" ]; then \
-			echo "  FAILED: $${LINKTO} is outside of current directory." >&2; \
-			continue; \
-		fi; \
-		if [ ! -e "$${LINKTO}" ]; then \
-			echo "  LINK $${LINKTO} -> $${LINKFROM}"; \
-			ln -s "$${LINKFROM}" "$${LINKTO}" || \
-				echo "FAILED: Could not create link." >&2; \
+		elif [ ! -e "$$SYMLINK" ]; then \
+			echo -e "\tLINK $$SYMLINK -> $$(dirname $$REALPATH)"; \
+			ln -s $$(dirname $$REALPATH) $$SYMLINK; \
 		else \
-			echo  "  FAILED: $${LINKTO} exists as a file or directory." >&2; \
-		fi; \
+			echo -e "\tFAILED: $$SYMLINK exists"; \
+		fi \
 	done
 
 clean-symlink:
-	if [ -z "$(SYMLINK_LIST)" ]; then \
-		echo "No site-local symbolic links to clean."; \
-		exit 0; \
-	fi; \
-	echo "Removing site-local symbolic links from tree.."; \
-	for link in $(SYMLINK_LIST); do \
-		SYMLINK="$(top)/$$(head -n 1 "$${link}")"; \
-		if [ "$${SYMLINK}" = "$$(echo "$${SYMLINK}" | sed "s|^$(top)||")" ]; then \
-			echo "  FAILED: $${SYMLINK} is outside of current directory." >&2; \
-			continue; \
-		elif [ ! -L "$${SYMLINK}" ]; then \
-			echo "  $${SYMLINK} does not exist - skipping"; \
-			continue; \
-		fi; \
-		if [ -L "$${SYMLINK}" ]; then \
-			REALDIR="$$(realpath "$${link}")"; \
-			echo "  UNLINK $${link} (linked from $${REALDIR})"; \
-			rm "$${SYMLINK}"; \
-		fi; \
-	done; \
-	EXISTING_SYMLINKS="$$(find $(top) -type l | grep -v "3rdparty\|crossgcc" )"; \
-	if [ -z "$${EXISTING_SYMLINKS}" ]; then \
-		echo "  No remaining symbolic links found in tree."; \
-	else \
-		echo "  Remaining symbolic links found:"; \
-		for link in $${EXISTING_SYMLINKS}; do \
-			echo "    $${link}"; \
-		done; \
-	fi
-
-cleanall-symlink:
-	echo "Deleting all symbolic links in the coreboot tree (excluding 3rdparty & crossgcc)"; \
-	EXISTING_SYMLINKS="$$(find $(top) -type l | grep -v "3rdparty\|crossgcc" )"; \
-	for link in $${EXISTING_SYMLINKS}; do \
-		if [ -L "$${link}" ]; then \
-			REALDIR="$$(realpath "$${link}")"; \
-			echo "  UNLINK $${link} (linked from $${REALDIR})"; \
-			rm "$${link}"; \
-		fi; \
+	@echo "Deleting symbolic link";\
+	EXISTING_SYMLINKS=`find -L ./src -xtype l | grep -v 3rdparty`; \
+	for link in $$EXISTING_SYMLINKS; do \
+		echo -e "\tUNLINK $$link"; \
+		rm "$$link"; \
 	done
 
 clean-for-update:
@@ -591,5 +537,4 @@ distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils
 	rm -f abuild*.xml junit.xml* util/lint/junit.xml
 
 .PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean sphinx sphinx-lint
-.PHONY: ctags-project cscope-project clean-ctags
-.PHONY: symlink clean-symlink cleanall-symlink
+.PHONY: ctags-project cscope-project clean-ctags symlink clean-symlink

Makefile.mk

@@ -90,23 +90,13 @@ show_coreboot: | files_added
 .PHONY: show_notices
 show_notices:: | show_coreboot
 
-# This rule allows the site-local makefile to run before starting the actual
-# coreboot build. It should not be used in the regular coreboot makefiles.
-# Note: This gets run after the immediate makefile code like updating the
-# submodules, but before any other targets.
-.PHONY: site-local-target
-site-local-target::
-
 #######################################################################
 # our phony targets
 PHONY+= clean-abuild coreboot check-style build_complete
 
 #######################################################################
 # root source directories of coreboot
-# site-local Makefile.mk must go first to override default locations (for binaries etc.)
-subdirs-y := site-local
-
-subdirs-y += src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
 subdirs-$(CONFIG_EC_ACPI) += src/ec/intel
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))
@@ -122,6 +112,8 @@ subdirs-y += src/mainboard/$(MAINBOARDDIR)
 subdirs-y += src/security
 subdirs-y += payloads payloads/external
 subdirs-$(CONFIG_SBOM) += src/sbom
+
+subdirs-y += site-local
 subdirs-y += util/checklist util/testing
 
 #######################################################################
@@ -178,7 +170,7 @@ _int-multiply2=$(shell expr $(call _toint,$1) \* $(call _toint,$2))
 int-multiply=$(if $(filter 1,$(words $1)),$(strip $1),$(call int-multiply,$(call _int-multiply2,$(word 1,$1),$(word 2,$1)) $(wordlist 3,$(words $1),$1)))
 int-divide=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) / $(call _toint,$(word 2,$1))))
 int-remainder=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) % $(call _toint,$(word 2,$1))))
-int-shift-left=$(shell echo -n $$(($(call _toint,$(word 1, $1)) << $(call _toint,$(word 2, $1)))))
+int-shift-left=$(shell echo "$(call _toint,$(word 1, $1)) * (2 ^ $(call _toint,$(word 2, $1)))" | bc)
 int-lt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) \< $(call _toint,$(word 2,$1))))
 int-gt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) \> $(call _toint,$(word 2,$1))))
 int-eq=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) = $(call _toint,$(word 2,$1))))
@@ -482,11 +474,7 @@ COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
 COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION
 endif
 
-CPPFLAGS_common := -Isrc
-CPPFLAGS_common += -Isrc/include
-CPPFLAGS_common += -Isrc/commonlib/include
-CPPFLAGS_common += -Isrc/commonlib/bsd/include
-CPPFLAGS_common += -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -I$(obj)
 VBOOT_SOURCE ?= 3rdparty/vboot
 CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
@@ -504,62 +492,31 @@ ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL)$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE),y)
 CPPFLAGS_ramstage += -Isrc/device/oprom/include
 endif
 
-CFLAGS_common += -pipe
-CFLAGS_common += -g
-CFLAGS_common += -nostdinc
-CFLAGS_common += -std=gnu11
-CFLAGS_common += -nostdlib
-CFLAGS_common += -Wall
-CFLAGS_common += -Wundef
-CFLAGS_common += -Wstrict-prototypes
-CFLAGS_common += -Wmissing-prototypes
-CFLAGS_common += -Wwrite-strings
-CFLAGS_common += -Wredundant-decls
-CFLAGS_common += -Wno-trigraphs
-CFLAGS_common += -Wimplicit-fallthrough
-CFLAGS_common += -Wshadow
-CFLAGS_common += -Wdate-time
-CFLAGS_common += -Wtype-limits
-CFLAGS_common += -Wvla
-CFLAGS_common += -Wold-style-definition
-CFLAGS_common += -Wdangling-else
-CFLAGS_common += -Wmissing-include-dirs
-CFLAGS_common += -fno-common
-CFLAGS_common += -ffreestanding
-CFLAGS_common += -fno-builtin
-CFLAGS_common += -fomit-frame-pointer
-CFLAGS_common += -fstrict-aliasing
-CFLAGS_common += -ffunction-sections
-CFLAGS_common += -fdata-sections
-CFLAGS_common += -fno-pie
+CFLAGS_common += -pipe -g -nostdinc -std=gnu11
+CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
+CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
+CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition
+CFLAGS_common += -Wdangling-else -Wmissing-include-dirs
+CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
+CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
 CFLAGS_common += -Wstring-compare
 ifeq ($(CONFIG_COMPILER_GCC),y)
 CFLAGS_common += -Wold-style-declaration
-CFLAGS_common += -Wcast-function-type
 # Don't add these GCC specific flags when running scan-build
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
 CFLAGS_common += -Wnull-dereference
-CFLAGS_common += -Wlogical-op
-CFLAGS_common += -Wduplicated-cond
-CFLAGS_common += -Wno-array-compare
+CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
 endif
 endif
 
 ADAFLAGS_common += -gnatp
-ADAFLAGS_common += -Wuninitialized
-ADAFLAGS_common += -Wall
-ADAFLAGS_common += -Werror
-ADAFLAGS_common += -pipe
-ADAFLAGS_common += -g
-ADAFLAGS_common += -nostdinc
-ADAFLAGS_common += -Wstrict-aliasing
-ADAFLAGS_common += -Wshadow
-ADAFLAGS_common += -fno-common
-ADAFLAGS_common += -fomit-frame-pointer
-ADAFLAGS_common += -ffunction-sections
-ADAFLAGS_common += -fdata-sections
+ADAFLAGS_common += -Wuninitialized -Wall -Werror
+ADAFLAGS_common += -pipe -g -nostdinc
+ADAFLAGS_common += -Wstrict-aliasing -Wshadow
+ADAFLAGS_common += -fno-common -fomit-frame-pointer
+ADAFLAGS_common += -ffunction-sections -fdata-sections
 ADAFLAGS_common += -fno-pie
 # Ada warning options:
 #
@@ -599,11 +556,7 @@ ADAFLAGS_common += -gnatwa.eeD.HHTU.U.W.Y
 # Disable style checks for now
 ADAFLAGS_common += -gnatyN
 
-LDFLAGS_common := --gc-sections
-LDFLAGS_common += -nostdlib
-LDFLAGS_common += --nmagic
-LDFLAGS_common += -static
-LDFLAGS_common += -z noexecstack
+LDFLAGS_common := --gc-sections -nostdlib --nmagic -static
 
 # Workaround for RISC-V linker bug, merge back into above line when fixed.
 # https://sourceware.org/bugzilla/show_bug.cgi?id=27180
@@ -1314,15 +1267,6 @@ ifeq ($(CONFIG_CBFS_VERIFICATION),y)
 	fi
 endif # CONFIG_CBFS_VERIFICATION
 
-define link_stage
-# $1 stage name
-
-$$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs)
-	@printf "    LINK       $$(subst $$(obj)/,,$$(@))\n"
-	$$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $(call src-to-obj,$(1),$(CONFIG_MEMLAYOUT_LD_FILE))
-
-endef
-
 ifeq ($(CONFIG_SEPARATE_ROMSTAGE),y)
 cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage
 $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf
@@ -1332,6 +1276,15 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y)
 $(CONFIG_CBFS_PREFIX)/romstage-options := -b 0
 endif
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
+# Use a 64 byte alignment to provide a minimum alignment
+# requirement for the overall romstage. While the first object within
+# romstage could have a 4 byte minimum alignment that doesn't mean the linker
+# won't decide the entire section should be aligned to a larger value. In the
+# future cbfstool should add XIP files proper and honor the alignment
+# requirements of the program segment.
+#
+# Make sure that segment for .car.data is ignored while adding romstage.
+$(CONFIG_CBFS_PREFIX)/romstage-align := 64
 ifeq ($(CONFIG_NO_XIP_EARLY_STAGES),y)
 $(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data"
 else

configs/builder/config.intel.crb.avc

@@ -1,50 +0,0 @@
-# Type this in coreboot root directory to get a working .config:
-#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc
-
-#
-# [RO] Board Configurations
-#
-CONFIG_VENDOR_INTEL=y
-CONFIG_BOARD_INTEL_AVENUECITY_CRB=y
-
-CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
-CONFIG_CONFIGURABLE_RAMSTAGE=y
-
-CONFIG_NO_GFX_INIT=y
-
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_PAYLOAD_LINUX=y
-
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_CONSOLE_SERIAL_115200=y
-
-#
-# [RW] IFWI Ingredients
-#
-CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/avenuecity/ucode.mcb"
-CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd"
-CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/"
-
-CONFIG_PAYLOAD_FILE="site-local/avenuecity/linuxboot_bzImage"
-CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
-
-#
-# [RW] Debug Settings
-#
-CONFIG_CONSOLE_POST=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
-
-CONFIG_VERIFY_HOBS=y
-CONFIG_DISPLAY_MTRRS=y
-
-CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
-CONFIG_DISPLAY_FSP_HEADER=y
-
-CONFIG_HAVE_DEBUG_GPIO=y
-CONFIG_DEBUG_GPIO=y

configs/builder/config.intel.crb.bnc

@@ -1,50 +0,0 @@
-# Type this in coreboot root directory to get a working .config:
-#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc
-
-#
-# [RO] Board Configurations
-#
-CONFIG_VENDOR_INTEL=y
-CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB=y
-
-CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
-CONFIG_CONFIGURABLE_RAMSTAGE=y
-
-CONFIG_NO_GFX_INIT=y
-
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_PAYLOAD_LINUX=y
-
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_CONSOLE_SERIAL_115200=y
-
-#
-# [RW] IFWI Ingredients
-#
-CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb"
-CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
-CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
-
-CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage"
-CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
-
-#
-# [RW] Debug Settings
-#
-CONFIG_CONSOLE_POST=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
-
-CONFIG_VERIFY_HOBS=y
-CONFIG_DISPLAY_MTRRS=y
-
-CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
-CONFIG_DISPLAY_FSP_HEADER=y
-
-CONFIG_HAVE_DEBUG_GPIO=y
-CONFIG_DEBUG_GPIO=y

configs/config.protectli_vp4630_vp4650

@@ -0,0 +1,13 @@
+CONFIG_VENDOR_PROTECTLI=y
+CONFIG_BOARD_PROTECTLI_VP4630_VP4650=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_SMMSTORE_SIZE=0x40000
+CONFIG_TPM2=y
+CONFIG_POST_IO_PORT=0x80
+CONFIG_PAYLOAD_EDK2=y
+CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
+CONFIG_EDK2_BOOT_TIMEOUT=6
+CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
+# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
+CONFIG_EDK2_SD_MMC_TIMEOUT=10
+CONFIG_EDK2_SERIAL_SUPPORT=y

configs/config.protectli_vp4670

@@ -1,5 +1,5 @@
 CONFIG_VENDOR_PROTECTLI=y
-CONFIG_BOARD_PROTECTLI_VP46XX=y
+CONFIG_BOARD_PROTECTLI_VP4670=y
 CONFIG_TPM_MEASURED_BOOT=y
 CONFIG_SMMSTORE_SIZE=0x40000
 CONFIG_TPM2=y

configs/config.sifive_hifive-unleashed.opensbi

@@ -1,3 +0,0 @@
-CONFIG_VENDOR_SIFIVE=y
-CONFIG_BOARD_SIFIVE_HIFIVE_UNLEASHED=y
-CONFIG_RISCV_OPENSBI=y

payloads/Makefile.mk

@@ -28,7 +28,6 @@ payloads/external/edk2 \
 payloads/external/GRUB2 \
 payloads/external/LinuxBoot \
 payloads/external/skiboot \
-payloads/external/leanefi \
 payloads/external/coreDOOM \
 
 force-payload:

payloads/external/LinuxBoot/Makefile

@@ -33,7 +33,7 @@ endif
 
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
 
-build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage build/initramfs | build
+build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage | build
 	cp $< $@
 
 else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)

payloads/external/Makefile.mk

@@ -381,7 +381,7 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT)
 	CONFIG_HAS_SCRIPT=$(CONFIG_IPXE_ADD_SCRIPT) \
 	CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \
 	CONFIG_IPXE_HAS_HTTPS=$(CONFIG_IPXE_HAS_HTTPS) \
-	CONFIG_IPXE_TRUST_CMD=$(CONFIG_IPXE_TRUST_CMD)
+	MFLAGS= MAKEFLAGS=
 
 # LinuxBoot
 LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86)        = x86_32
@@ -435,13 +435,6 @@ payloads/external/skiboot/build/skiboot.elf:
 	$(MAKE) -C payloads/external/skiboot all \
 		CONFIG_SKIBOOT_GIT_REPO=$(CONFIG_SKIBOOT_GIT_REPO) \
 		CONFIG_SKIBOOT_REVISION=$(CONFIG_SKIBOOT_REVISION)
-
-# leanefi
-
-payloads/external/leanefi/leanefi/build/leanefi.elf: FORCE $(DOTCONFIG)
-	$(MAKE) -C payloads/external/leanefi
-FORCE: ;
-
 # COREDOOM
 
 payloads/external/coreDOOM/coredoom/doomgeneric/coredoom.elf coredoom:

payloads/external/edk2/Kconfig

@@ -319,7 +319,7 @@ config EDK2_USE_LAPIC_TIMER
 
 config EDK2_CUSTOM_BUILD_PARAMS
 	string "edk2 additional custom build parameters"
-	default ""
+	default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2
 	help
 	  edk2 has build options that are not modified by coreboot, and these can be
 	  found in `UefiPayloadPkg/UefiPayloadPkg.dsc`. Forks may also support

payloads/external/edk2/Makefile

@@ -37,8 +37,6 @@ BUILD_STR += -s
 endif
 endif
 
-BUILD_STR += -D BUILD_ARCH=X64
-
 #
 # EDK II (edk2/master) has the following build options relevant to coreboot:
 #
@@ -69,10 +67,8 @@ endif
 ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y)
 BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
 endif
-# VARIABLE_SUPPORT		= EMU
 # MAX_VARIABLE_SIZE		= 0x10000
 ifeq ($(CONFIG_SMMSTORE_V2),y)
-BUILD_STR += -D VARIABLE_SUPPORT=SMMSTORE
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize=0x8000
 endif
 # PCIE_BASE_ADDRESS		= 0
@@ -224,7 +220,7 @@ logo: $(EDK2_PATH)
 			BMP3:$(EDK2_PATH)/MdeModulePkg/Logo/Logo.bmp;; \
 	esac \
 
-gop_driver: $(EDK2_PATH)
+gop_driver:
 	if [ -n "$(CONFIG_EDK2_GOP_DRIVER)" ]; then \
 		echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \
 		cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/UefiPayloadPkg/IntelGopDriver.efi; \

payloads/external/iPXE/Kconfig

@@ -108,16 +108,7 @@ config IPXE_HAS_HTTPS
 	  Enable HTTPS protocol, which allows you to encrypt all communication
 	  with a web server and to verify the server's identity
 
-config IPXE_TRUST_CMD
-	bool "Enable TRUST commands"
-	default y
-	help
-	  Enable imgverify and imgtrust commands, which allow you to verify
-	  digital signature of file prior loading it, and restrict to loading
-	  trusted files only.
-
 endif # BUILD_IPXE
-
 endmenu
 
 endif # PXE

payloads/external/iPXE/Makefile

@@ -52,9 +52,6 @@ endif
 ifeq ($(CONFIG_IPXE_HAS_HTTPS),y)
 	sed -i'' 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h"
 endif
-ifeq ($(CONFIG_IPXE_TRUST_CMD),y)
-	sed -i'' 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h"
-endif
 
 build: config $(CONFIG_SCRIPT)
 ifeq ($(CONFIG_HAS_SCRIPT),y)

payloads/external/leanefi/Kconfig

@@ -1,60 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-if PAYLOAD_LEANEFI
-
-menu "leanEFI configuration"
-
-config PAYLOAD_FILE
-	string
-	default "payloads/external/leanefi/leanefi/build/leanefi.elf"
-
-config LEANEFI_EFI_ECPT
-	bool
-	default y if ARCH_ARM64
-
-config LEANEFI_HEAP_SIZE
-	int "Heap size"
-	default 131072
-	help
-	  This is the heap size (malloc'able size) available
-	  to the payload.
-
-	  If unsure, set to 131072 (128K)
-
-config LEANEFI_STACK_SIZE
-	int "Stack size"
-	default 16384
-	help
-	  This is the stack size available to the payload.
-
-	  If unsure, set to 16384 (16K)
-
-config LEANEFI_BASE_ADDRESS
-	hex "Base address"
-	default 0x62000000 if BOARD_EMULATION_QEMU_AARCH64
-	#default 0x10023300000 if BOARD_EMULATION_QEMU_SBSA
-	help
-	  This is the base address for the payload.
-
-config LEANEFI_PAYLOAD
-	bool "Add a payload"
-	default y
-	help
-	  If selected leanEFI will start a payload.
-	  This option should only be unselected for debug purposes.
-
-config LEANEFI_PAYLOAD_PATH
-	string "path to leanefi payload"
-	depends on LEANEFI_PAYLOAD
-
-config LEANEFI_FDT
-	bool "Add an FDT that is propagated as EFI configuration table"
-	default y if BOARD_EMULATION_QEMU_AARCH64
-
-config LEANEFI_FDT_PATH
-	string "path to FDT"
-	depends on LEANEFI_FDT
-
-endmenu
-
-endif

payloads/external/leanefi/Kconfig.name

@@ -1,8 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-config PAYLOAD_LEANEFI
-	bool "leanefi"
-	depends on ARCH_ARM64
-	help
-	  Select this option if you want to build a coreboot image
-	  with an leanefi payload.

payloads/external/leanefi/Makefile

@@ -1,23 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-unexport KCONFIG_AUTOHEADER
-unexport KCONFIG_AUTOCONFIG
-unexport KCONFIG_DEPENDENCIES
-unexport KCONFIG_SPLITCONFIG
-unexport KCONFIG_TRISTATE
-unexport KCONFIG_NEGATIVES
-unexport $(COREBOOT_EXPORTS)
-
-build: leanefi
-	$(MAKE) -C leanefi
-
-leanefi:
-	git clone "https://review.coreboot.org/leanefi"
-
-distclean:
-	rm -rf leanefi
-
-clean:
-	rm -rf leanefi/build
-
-.PHONY: build clean distclean

payloads/libpayload/Kconfig

@@ -106,22 +106,17 @@ menu "Architecture Options"
 
 choice
         prompt "Target Architecture"
-        default ARCH_X86_32
+        default ARCH_X86
 
 config ARCH_ARM
         bool "ARM"
         help
           Support the ARM architecture
 
-config ARCH_X86_32
-        bool "x86_32"
+config ARCH_X86
+        bool "x86"
         help
-          Support the x86_32 architecture
-
-config ARCH_X86_64
-        bool "x86_64"
-        help
-          Support the x86_64 architecture
+          Support the x86 architecture
 
 config ARCH_ARM64
         bool "ARM64"
@@ -138,12 +133,6 @@ config ARCH_MOCK
 
 endchoice
 
-config ARCH_X86
-	bool
-	default y if ARCH_X86_32 || ARCH_X86_64
-	help
-	  Support the x86 architecture
-
 config MULTIBOOT
 	bool "Multiboot header support"
 	depends on ARCH_X86

payloads/libpayload/Makefile

@@ -118,8 +118,7 @@ ARCH-y := $(ARCHDIR-y)
 # override here.
 ARCH-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCH-$(CONFIG_LP_ARCH_ARM64)   := arm64
-ARCH-$(CONFIG_LP_ARCH_X86_32)  := x86_32
-ARCH-$(CONFIG_LP_ARCH_X86_64)  := x86_64
+ARCH-$(CONFIG_LP_ARCH_X86)     := x86_32
 ARCH-$(CONFIG_LP_ARCH_MOCK)    := mock
 
 # Five cases where we don't need fully populated $(obj) lists:

payloads/libpayload/Makefile.mk

@@ -56,6 +56,7 @@ classes-$(CONFIG_LP_REMOTEGDB) += libgdb
 classes-$(CONFIG_LP_VBOOT_LIB) += vboot_fw
 classes-$(CONFIG_LP_VBOOT_LIB) += tlcl
 libraries := $(classes-y)
+classes-y += head.o
 
 subdirs-y := arch/$(ARCHDIR-y)
 subdirs-y += crypto libc drivers libpci gdb
@@ -96,7 +97,7 @@ $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) $(obj)/libpayload.config
 	cmp $@ $< 2>/dev/null || cp $< $@
 
 library-targets = $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a
-lib: $$(library-targets) $(obj)/libpayload.ldscript
+lib: $$(library-targets) $(obj)/head.o
 
 extract_nth=$(word $(1), $(subst |, ,$(2)))
 
@@ -115,16 +116,17 @@ $(obj)/%.a: $$(%-objs)
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"
 	printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M
 
-$(obj)/libpayload.ldscript: arch/$(ARCHDIR-y)/libpayload.ldscript $(obj)/libpayload-config.h
-	@printf "  LDSCRIPT  $@\n"
-	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -E -P -x assembler-with-cpp -undef -o $@ $<
+$(obj)/head.o: $(obj)/arch/$(ARCHDIR-y)/head.head.o.o
+	printf "    CP         $(subst $(CURDIR)/,,$(@))\n"
+	cp $^ $@
 
 install: real-target
 	printf "    INSTALL    $(DESTDIR)/libpayload/lib\n"
 	install -m 755 -d $(DESTDIR)/libpayload/lib
 	install -m 644 $(library-targets) $(DESTDIR)/libpayload/lib/
-	install -m 644 $(obj)/libpayload.ldscript $(DESTDIR)/libpayload/lib/
+	install -m 644 arch/$(ARCHDIR-y)/libpayload.ldscript $(DESTDIR)/libpayload/lib/
 	install -m 755 -d $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
+	install -m 644 $(obj)/head.o $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
 	printf "    INSTALL    $(DESTDIR)/libpayload/include\n"
 	install -m 755 -d $(DESTDIR)/libpayload/include
 	find include -type d -exec install -m755 -d $(DESTDIR)/libpayload/{} \;

payloads/libpayload/arch/arm/Makefile.mk

@@ -29,7 +29,7 @@
 CFLAGS += -mthumb -march=armv7-a
 arm_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated
 
-libc-y += head.S
+head.o-y += head.S
 libc-y += eabi_compat.c
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
@@ -44,4 +44,5 @@ libc-$(CONFIG_LP_GPL) += memcpy.S memset.S memmove.S
 libgdb-y += gdb.c
 
 # Add other classes here when you put assembly files into them!
+head.o-S-ccopts += $(arm_asm_flags)
 libc-S-ccopts += $(arm_asm_flags)

payloads/libpayload/arch/arm64/Makefile.mk

@@ -29,7 +29,7 @@
 CFLAGS += -march=armv8-a
 arm64_asm_flags =
 
-libc-y += head.S
+head.o-y += head.S
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
 libc-y += virtual.c
@@ -42,4 +42,5 @@ libc-y += mmu.c
 libgdb-y += gdb.c
 
 # Add other classes here when you put assembly files into them!
-libc-S-ccopts += $(arm64_asm_flags)
+ head.o-S-ccopts += $(arm64_asm_flags)
+ libc-S-ccopts += $(arm64_asm_flags)

payloads/libpayload/arch/arm64/cpu.S

@@ -41,9 +41,6 @@
 	mov	w10, #0				// w10 = 2 * cache level
 	mov	w8, #1				// w8 = constant 0b1
 
-	mrs	x12, id_aa64mmfr2_el1		// read ID_AA64MMFR2_EL1
-	ubfx	x12, x12, #20, #4		// [23:20] - CCIDX support
-
 1:	//next_level
 	add	w2, w10, w10, lsr #1		// calculate 3 * cache level
 	lsr	w1, w0, w2			// extract 3-bit cache type for this level
@@ -55,14 +52,8 @@
 	mrs	x1, ccsidr_el1			// w1 = read ccsidr
 	and	w2, w1, #7			// w2 = log2(linelen_bytes) - 4
 	add	w2, w2, #4			// w2 = log2(linelen_bytes)
-
-	cbz	x12, 11f			// check FEAT_CCIDX for associativity
-						// branch to 11 if FEAT_CCIDX is not implemented
-	ubfx	x4, x1, #3, #21			// x4 = associativity CCSIDR_EL1[23:3]
-	b	12f
-11:
-	ubfx	x4, x1, #3, #10			// x4 = associativity CCSIDR_EL1[12:3]
-12:
+	ubfx	w4, w1, #3, #10			// w4 = associativity - 1 (also
+						// max way number)
 	clz	w5, w4				// w5 = 32 - log2(ways)
 						// (bit position of way in DC)
 	lsl	w9, w4, w5			// w9 = max way number
@@ -70,13 +61,7 @@
 	lsl	w16, w8, w5			// w16 = amount to decrement (way
 						// number per iteration)
 2:	//next_way
-	cbz	x12, 21f			// check FEAT_CCIDX for numsets
-						// branch to 21 if FEAT_CCIDX is not implemented
-	ubfx	x7, x1, #32, #24		// x7(w7) = numsets CCSIDR_EL1[55:32]
-	b	22f
-21:
-	ubfx	w7, w1, #13, #15		// w7 = numsets CCSIDR_EL1[27:13]
-22:
+	ubfx	w7, w1, #13, #15		// w7 = max set #, right aligned
 	lsl	w7, w7, w2			// w7 = max set #, DC aligned
 	lsl	w17, w8, w2			// w17 = amount to decrement (set
 						// number per iteration)

payloads/libpayload/arch/mock/Makefile.mk

@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
+head.o-y += head.c
+
 libc-y += virtual.c
 
 CFLAGS += -Wno-address-of-packed-member

payloads/libpayload/arch/mock/head.c

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This file is empty on purpose. It should not be used. */

payloads/libpayload/arch/x86/Makefile.mk

@@ -27,26 +27,16 @@
 ##
 
 ifneq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y)
-ifeq ($(CONFIG_LP_ARCH_X86_64),y)
-CFLAGS += -mpreferred-stack-boundary=4
-else
 CFLAGS += -mpreferred-stack-boundary=2
 endif
-endif
 
-libc-$(CONFIG_LP_ARCH_X86_32)  += head.S
-libc-$(CONFIG_LP_ARCH_X86_64)  += head_64.S
-libc-$(CONFIG_LP_ARCH_X86_64) += pt.S
+head.o-y += head.S
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
-libc-y += virtual.c
+libc-y += exec.S virtual.c
 libc-y += selfboot.c cache.c
-libc-y += exception.c
+libc-y += exception_asm.S exception.c
 libc-y += delay.c
-libc-$(CONFIG_LP_ARCH_X86_32) += exec.c
-libc-$(CONFIG_LP_ARCH_X86_32) += exec.S
-libc-$(CONFIG_LP_ARCH_X86_32) += exception_asm.S
-libc-$(CONFIG_LP_ARCH_X86_64) += exception_asm_64.S
 
 # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed.
 libc-$(CONFIG_LP_GPL) += string.c

payloads/libpayload/arch/x86/exception.c

@@ -34,13 +34,7 @@
 
 #define IF_FLAG				(1 << 9)
 
-#if CONFIG(LP_ARCH_X86_64)
-#define REGISTER_FMT "0x%016zx"
-#else
-#define REGISTER_FMT "0x%08zx"
-#endif
-
-u8 exception_stack[0x400] __aligned(16);
+u32 exception_stack[0x400] __attribute__((aligned(8)));
 
 static interrupt_handler handlers[256];
 
@@ -113,15 +107,13 @@ static void dump_stack(uintptr_t addr, size_t bytes)
 {
 	int i, j;
 	const int line = 8;
-	uint32_t *ptr = (uint32_t *)((uintptr_t)addr & ~(line * sizeof(*ptr) - 1));
+	uint32_t *ptr = (uint32_t *)(addr & ~(line * sizeof(*ptr) - 1));
 
 	printf("Dumping stack:\n");
 	for (i = bytes / sizeof(*ptr); i >= 0; i -= line) {
 		printf("%p: ", ptr + i);
-		for (j = i; j < i + line; j++) {
-			if ((uintptr_t)(ptr + j) >= addr && (uintptr_t)(ptr + j) < addr + bytes)
-				printf("%08x ", *(ptr + j));
-		}
+		for (j = i; j < i + line; j++)
+			printf("%08x ", *(ptr + j));
 		printf("\n");
 	}
 }
@@ -151,27 +143,17 @@ static void dump_exception_state(void)
 		break;
 	}
 	printf("\n");
-	printf("REG_IP:    " REGISTER_FMT "\n", exception_state->regs.reg_ip);
-	printf("REG_FLAGS: " REGISTER_FMT "\n", exception_state->regs.reg_flags);
-	printf("REG_AX:    " REGISTER_FMT "\n", exception_state->regs.reg_ax);
-	printf("REG_BX:    " REGISTER_FMT "\n", exception_state->regs.reg_bx);
-	printf("REG_CX:    " REGISTER_FMT "\n", exception_state->regs.reg_cx);
-	printf("REG_DX:    " REGISTER_FMT "\n", exception_state->regs.reg_dx);
-	printf("REG_SP:    " REGISTER_FMT "\n", exception_state->regs.reg_sp);
-	printf("REG_BP:    " REGISTER_FMT "\n", exception_state->regs.reg_bp);
-	printf("REG_SI:    " REGISTER_FMT "\n", exception_state->regs.reg_si);
-	printf("REG_DI:    " REGISTER_FMT "\n", exception_state->regs.reg_di);
-#if CONFIG(LP_ARCH_X86_64)
-	printf("REG_R8:    0x%016zx\n", exception_state->regs.reg_r8);
-	printf("REG_R9:    0x%016zx\n", exception_state->regs.reg_r9);
-	printf("REG_R10:   0x%016zx\n", exception_state->regs.reg_r10);
-	printf("REG_R11:   0x%016zx\n", exception_state->regs.reg_r11);
-	printf("REG_R12:   0x%016zx\n", exception_state->regs.reg_r12);
-	printf("REG_R13:   0x%016zx\n", exception_state->regs.reg_r13);
-	printf("REG_R14:   0x%016zx\n", exception_state->regs.reg_r14);
-	printf("REG_R15:   0x%016zx\n", exception_state->regs.reg_r15);
-#endif
+	printf("EIP:    0x%08x\n", exception_state->regs.eip);
 	printf("CS:     0x%04x\n", exception_state->regs.cs);
+	printf("EFLAGS: 0x%08x\n", exception_state->regs.eflags);
+	printf("EAX:    0x%08x\n", exception_state->regs.eax);
+	printf("ECX:    0x%08x\n", exception_state->regs.ecx);
+	printf("EDX:    0x%08x\n", exception_state->regs.edx);
+	printf("EBX:    0x%08x\n", exception_state->regs.ebx);
+	printf("ESP:    0x%08x\n", exception_state->regs.esp);
+	printf("EBP:    0x%08x\n", exception_state->regs.ebp);
+	printf("ESI:    0x%08x\n", exception_state->regs.esi);
+	printf("EDI:    0x%08x\n", exception_state->regs.edi);
 	printf("DS:     0x%04x\n", exception_state->regs.ds);
 	printf("ES:     0x%04x\n", exception_state->regs.es);
 	printf("SS:     0x%04x\n", exception_state->regs.ss);
@@ -182,7 +164,7 @@ static void dump_exception_state(void)
 void exception_dispatch(void)
 {
 	die_if(exception_state->vector >= ARRAY_SIZE(handlers),
-	       "Invalid vector %zu\n", exception_state->vector);
+	       "Invalid vector %u\n", exception_state->vector);
 
 	u8 vec = exception_state->vector;
 
@@ -202,7 +184,7 @@ void exception_dispatch(void)
 	       vec);
 
 	dump_exception_state();
-	dump_stack(exception_state->regs.reg_sp, 512);
+	dump_stack(exception_state->regs.esp, 512);
 	/* We don't call apic_eoi because we don't want to ack the interrupt and
 	   allow another interrupt to wake the processor. */
 	halt();
@@ -224,17 +206,6 @@ void set_interrupt_handler(u8 vector, interrupt_handler handler)
 	handlers[vector] = handler;
 }
 
-#if CONFIG(LP_ARCH_X86_64)
-static uint64_t eflags(void)
-{
-	uint64_t eflags;
-	asm volatile(
-		"pushfq\n\t"
-		"popq %0\n\t"
-	: "=rm" (eflags));
-	return eflags;
-}
-#else
 static uint32_t eflags(void)
 {
 	uint32_t eflags;
@@ -244,7 +215,6 @@ static uint32_t eflags(void)
 	: "=rm" (eflags));
 	return eflags;
 }
-#endif
 
 void enable_interrupts(void)
 {

payloads/libpayload/arch/x86/exception_asm_64.S

@@ -1,351 +0,0 @@
-/*
- *
- * Copyright 2024 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-	.align 16
-	.global exception_stack_end
-exception_stack_end:
-	.quad 0
-	.global exception_state
-exception_state:
-	.quad 0
-
-/* Some temporary variables which are used while saving exception state. */
-vector:
-	.quad 0
-error_code:
-	.quad 0
-old_rax:
-	.quad 0
-old_rcx:
-	.quad 0
-
-	.align 16
-
-/*
- * Each exception vector has a small stub associated with it which sets aside
- * the error code, if any, records which vector we entered from, and calls
- * the common exception entry point. Some exceptions have error codes and some
- * don't, so we have a macro for each type.
- */
-
-	.macro stub num
-exception_stub_\num:
-	movq $0, error_code
-	movq $\num, vector
-	jmp exception_common
-	.endm
-
-	.macro stub_err num
-exception_stub_\num:
-	pop error_code
-	movq $\num, vector
-	jmp exception_common
-	.endm
-
-	.altmacro
-	.macro user_defined_stubs from, to
-	stub \from
-	.if \to-\from
-	user_defined_stubs %(from+1),\to
-	.endif
-	.endm
-
-	stub 0
-	stub 1
-	stub 2
-	stub 3
-	stub 4
-	stub 5
-	stub 6
-	stub 7
-	stub_err 8
-	stub 9
-	stub_err 10
-	stub_err 11
-	stub_err 12
-	stub_err 13
-	stub_err 14
-	stub 15
-	stub 16
-	stub_err 17
-	stub 18
-	stub 19
-	stub 20
-	stub 21
-	stub 22
-	stub 23
-	stub 24
-	stub 25
-	stub 26
-	stub 27
-	stub 28
-	stub 29
-	stub_err 30
-	stub 31
-	/* Split the macro so we avoid a stack overflow. */
-	user_defined_stubs 32, 63
-	user_defined_stubs 64, 127
-	user_defined_stubs 128, 191
-	user_defined_stubs 192, 255
-
-exception_common:
-	/*
-	 * At this point, on x86-64, on the stack there is:
-	 * 0(%rsp) rip
-	 * 8(%rsp) cs
-	 * 16(%rsp) rflags
-	 * 24(%rsp) rsp
-	 * 32(%rsp) ss
-	 *
-	 * This section sets up the exception stack.
-	 * It saves the old stack pointer (rsp) to preserve RIP, CS, RFLAGS and SS.
-	 * Then sets up the new stack pointer to point to the exception stack area.
-	 */
-	movq %rax, old_rax
-	movq %rcx, old_rcx
-
-	mov %rsp, %rax
-	movq exception_stack_end, %rsp
-	/*
-	 * The `exception_state` struct is not 16-byte aligned.
-	 * Push an extra 8 bytes to ensure the stack pointer
-	 * is 16-byte aligned before calling exception_dispatch.
-	 */
-	push $0
-
-	/*
-	 * Push values onto the top of the exception stack to form an
-	 * exception state structure.
-	 */
-	push vector
-	push error_code
-
-	/* push of the gs, fs, es, ds, ss and cs */
-	mov %gs, %rcx
-	movl %ecx, -4(%rsp)   /* gs */
-	mov %fs, %rcx
-	movl %ecx, -8(%rsp)   /* fs */
-	movl $0, -12(%rsp)    /* es */
-	movl $0, -16(%rsp)    /* ds */
-	movq 32(%rax), %rcx
-	movl %ecx, -20(%rsp)  /* ss */
-	movq 8(%rax), %rcx
-	movl %ecx, -24(%rsp)  /* cs */
-	sub $24, %rsp
-
-	push 16(%rax)         /* rflags */
-	push (%rax)           /* rip */
-	push %r15
-	push %r14
-	push %r13
-	push %r12
-	push %r11
-	push %r10
-	push %r9
-	push %r8
-	push 24(%rax)         /* rsp */
-	push %rbp
-	push %rdi
-	push %rsi
-	push %rdx
-	push old_rcx          /* rcx */
-	push %rbx
-	push old_rax          /* rax */
-
-	/*
-	 * Call the C exception handler. It will find the exception state
-	 * using the exception_state global pointer. Not
-	 * passing parameters means we don't have to worry about what ABI
-	 * is being used.
-	 */
-	mov %rsp, exception_state
-	call exception_dispatch
-
-	/*
-	 * Restore state from the exception state structure, including any
-	 * changes that might have been made.
-	 */
-	pop old_rax
-	pop %rbx
-	pop old_rcx
-	pop %rdx
-	pop %rsi
-	pop %rdi
-	pop %rbp
-	lea exception_stack, %rax
-	pop 24(%rax)          /* rsp */
-	pop %r8
-	pop %r9
-	pop %r10
-	pop %r11
-	pop %r12
-	pop %r13
-	pop %r14
-	pop %r15
-	pop (%rax)            /* rip */
-	pop 16(%rax)          /* rflags */
-
-	/* pop of the gs, fs, es, ds, ss and cs */
-	movl (%rsp), %ecx
-	movq %rcx, 8(%rax)    /* cs */
-	movl 4(%rsp), %ecx
-	movq %rcx, 32(%rax)   /* ss */
-	movl 16(%rsp), %ecx
-	mov %rcx, %fs         /* fs */
-	movl 20(%rsp), %ecx
-	mov %rcx, %gs         /* gs */
-
-	mov %rax, %rsp
-	movq old_rax, %rax
-	movq old_rcx, %rcx
-
-	iretq
-
-/*
- * We need segment selectors for the IDT, so we need to know where things are
- * in the GDT. We set one up here which is pretty standard and largely copied
- * from coreboot.
- */
-	.align 16
-gdt:
-	/* selgdt 0, unused */
-	.word 0x0000, 0x0000
-	.byte 0x00, 0x00, 0x00, 0x00
-
-	/* selgdt 8, unused */
-	.word 0x0000, 0x0000
-	.byte 0x00, 0x00, 0x00, 0x00
-
-	/* selgdt 0x10, flat 4GB code segment */
-	.word 0xffff, 0x0000
-	.byte 0x00, 0x9b, 0xcf, 0x00
-
-	/* selgdt 0x18, flat 4GB data segment */
-	.word 0xffff, 0x0000
-	.byte 0x00, 0x92, 0xcf, 0x00
-
-	/* selgdt 0x20, flat x64 code segment */
-	.word 0xffff, 0x0000
-	.byte 0x00, 0x9b, 0xaf, 0x00
-gdt_end:
-
-/* GDT pointer for use with lgdt */
-.global gdt_ptr
-gdt_ptr:
-	.word gdt_end - gdt - 1
-	.quad gdt
-
-	/*
-	 * Record the target and construct the actual entry at init time. This
-	 * is necessary because the linker doesn't want to construct the entry
-	 * for us.
-	 */
-	.macro interrupt_gate target
-	.word 0       /* patchable */
-	.word 0x20    /* Target code segment selector */
-	.word 0xee00  /* Present, Type 64-bit Interrupt Gate */
-	.word 0       /* patchable */
-	.quad \target /* patchable */
-	.endm
-
-	.altmacro
-	.macro	user_defined_gates from, to
-	interrupt_gate	exception_stub_\from
-	.if	\to-\from
-	user_defined_gates	%(from+1),\to
-	.endif
-	.endm
-
-	.align 16
-	.global idt
-idt:
-	interrupt_gate exception_stub_0
-	interrupt_gate exception_stub_1
-	interrupt_gate exception_stub_2
-	interrupt_gate exception_stub_3
-	interrupt_gate exception_stub_4
-	interrupt_gate exception_stub_5
-	interrupt_gate exception_stub_6
-	interrupt_gate exception_stub_7
-	interrupt_gate exception_stub_8
-	interrupt_gate exception_stub_9
-	interrupt_gate exception_stub_10
-	interrupt_gate exception_stub_11
-	interrupt_gate exception_stub_12
-	interrupt_gate exception_stub_13
-	interrupt_gate exception_stub_14
-	interrupt_gate exception_stub_15
-	interrupt_gate exception_stub_16
-	interrupt_gate exception_stub_17
-	interrupt_gate exception_stub_18
-	interrupt_gate exception_stub_19
-	interrupt_gate exception_stub_20
-	interrupt_gate exception_stub_21
-	interrupt_gate exception_stub_22
-	interrupt_gate exception_stub_23
-	interrupt_gate exception_stub_24
-	interrupt_gate exception_stub_25
-	interrupt_gate exception_stub_26
-	interrupt_gate exception_stub_27
-	interrupt_gate exception_stub_28
-	interrupt_gate exception_stub_29
-	interrupt_gate exception_stub_30
-	interrupt_gate exception_stub_31
-	user_defined_gates 32, 63
-	user_defined_gates 64, 127
-	user_defined_gates 128, 191
-	user_defined_gates 192, 255
-idt_end:
-
-/* IDT pointer for use with lidt */
-idt_ptr:
-	.word idt_end - idt - 1
-	.quad idt
-
-.section .text.exception_init_asm
-.globl exception_init_asm
-.type exception_init_asm, @function
-
-exception_init_asm:
-	/* Set up IDT entries */
-	mov $idt, %rax
-1:
-	movq 8(%rax), %rdi
-	movw %di, (%rax)   /* procedure entry point offset bits 0..15 */
-	shr $16, %rdi
-	movw %di, 6(%rax)  /* procedure entry point offset bits 16..31 */
-	shr $16, %rdi
-	movl %edi, 8(%rax) /* procedure entry point offset bits 32..63 */
-	movl $0, 12(%rax)  /* reserved */
-	add $16, %rax
-	cmp $idt_end, %rax
-	jne 1b
-
-	/* Load the IDT */
-	lidt idt_ptr
-	ret

payloads/libpayload/arch/x86/gdb.c

@@ -15,7 +15,6 @@
 #include <exception.h>
 #include <gdb.h>
 #include <libpayload.h>
-#include <stddef.h>
 
 static const u8 type_to_signal[] = {
 	[EXC_DE]  = GDB_SIGFPE,
@@ -54,15 +53,12 @@ void gdb_arch_init(void)
 
 void gdb_arch_enter(void)
 {
-	u8 *stack_pointer;
-#if CONFIG(LP_ARCH_X86_64)
-	asm volatile ("movq %%rsp, %0" : "=r"(stack_pointer));
-#else
-	asm volatile ("mov %%esp, %0" : "=r"(stack_pointer));
-#endif
+	u32 *esp;
+
+	asm volatile ("mov %%esp, %0" : "=r"(esp) );
 
 	/* Avoid reentrant exceptions, just call the hook if in one already. */
-	if (stack_pointer >= exception_stack && stack_pointer <= exception_stack_end)
+	if (esp >= exception_stack && esp <= exception_stack_end)
 		gdb_exception_hook(EXC_BP);
 	else
 		asm volatile ("int3");
@@ -70,12 +66,12 @@ void gdb_arch_enter(void)
 
 int gdb_arch_set_single_step(int on)
 {
-	const size_t tf_bit = 1 << 8;
+	const u32 tf_bit = 1 << 8;
 
 	if (on)
-		exception_state->regs.reg_flags |= tf_bit;
+		exception_state->regs.eflags |= tf_bit;
 	else
-		exception_state->regs.reg_flags &= ~tf_bit;
+		exception_state->regs.eflags &= ~tf_bit;
 
 	return 0;
 }

payloads/libpayload/arch/x86/head.S

@@ -29,7 +29,7 @@
 
 	.code32
 	.global _entry
-	.section .text._entry
+	.text
 	.align 4
 
 /*
@@ -38,14 +38,37 @@
  * change anything.
  */
 _entry:
+	jmp _init
 
-	/* Add multiboot header and jump around it when building with multiboot support. */
-#if CONFIG(LP_MULTIBOOT)
-	#include "multiboot_header.inc"
-#endif
+	.align 4
+
+#define MB_MAGIC 0x1BADB002
+#define MB_FLAGS 0x00010003
+
+mb_header:
+	.long MB_MAGIC
+	.long MB_FLAGS
+	.long -(MB_MAGIC + MB_FLAGS)
+	.long mb_header
+	.long _start
+	.long _edata
+	.long _end
+	.long _init
+
+/*
+ * This function saves off the previous stack and switches us to our
+ * own execution environment.
+ */
+_init:
 	/* No interrupts, please. */
 	cli
 
+#if CONFIG(LP_MULTIBOOT)
+	/* Store EAX and EBX */
+	movl %eax, loader_eax
+	movl %ebx, loader_ebx
+#endif
+
 	/* save pointer to coreboot tables */
 	movl 4(%esp), %eax
 	movl %eax, cb_header_ptr

payloads/libpayload/arch/x86/head_64.S

@@ -1,141 +0,0 @@
-/*
- *
- * Copyright (C) 2024 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#define IA32_EFER	0xC0000080
-#define  EFER_LME	(1 << 8)
-
-	.code32
-	.global _entry
-	.section .text._entry
-	.align 4
-
-/*
- * WARNING: Critical Code Section - 32/64-bit Compatibility
- * This code between `_entry` and `jnz _init64` is executed during system initialization.
- * It MUST function correctly regardless of whether the system is booting in:
- *   - 32-bit protected mode
- *   - 64-bit long mode
- * To achieve this, ONLY use instructions that produce identical binary output in both modes.
- * Thoroughly test ALL modifications to this section in BOTH 32-bit and 64-bit boot
- * environments.
- */
-
-_entry:
-
-	/* Add multiboot header and jump around it when building with multiboot support. */
-#if CONFIG(LP_MULTIBOOT)
-	#include "multiboot_header.inc"
-#endif
-	/* No interrupts, please. */
-	cli
-
-	movl $IA32_EFER, %ecx
-	rdmsr
-	testl $EFER_LME, %eax
-	jnz _init64
-
-	lgdt %cs:gdt_ptr
-
-	/* save pointer to coreboot tables */
-	movl 4(%esp), %eax
-	/*
-	 * NOTE: coreboot tables has passed over the top of the stack
-	 * while calling in protected mode.
-	 */
-	movl %eax, cb_header_ptr
-
-	call init_page_table
-	movl $pm4le, %eax
-
-	/* load identity mapped page tables */
-	movl %eax, %cr3
-
-	/* enable PAE */
-	movl %cr4, %eax
-	btsl $5, %eax
-	movl %eax, %cr4
-
-	/* enable long mode */
-	movl $(IA32_EFER), %ecx
-	rdmsr
-	btsl $8, %eax
-	wrmsr
-
-	/* enable paging */
-	movl %cr0, %eax
-	btsl $31, %eax
-	movl %eax, %cr0
-
-	/* Jump to selgdt 0x20, flat x64 code segment */
-	ljmp $0x20, $_entry64
-
-.code64
-.align 16
-_init64:
-	movabs	$gdt_ptr, %rax
-	lgdt	(%rax)
-
-	/*
-	 * Note: The `cb_header_ptr` has passed as the first argument
-	 * to the x86-64 calling convention.
-	 */
-	movq %rdi, cb_header_ptr
-
-	call init_page_table
-	movq $pm4le, %rax
-
-	/* load identity mapped page tables */
-	movq %rax, %cr3
-
-_entry64:
-	/* Store current stack pointer and set up new stack. */
-	movq %rsp, %rax
-	movabs	$_estack, %rsp
-
-	push %rax
-
-	fninit
-	movq %cr0, %rax
-	andq $0xFFFFFFFFFFFFFFFB, %rax	/* clear EM */
-	orq $0x00000022, %rax	/* set MP, NE */
-	movq %rax, %cr0
-
-	movq %cr4, %rax
-	orq $0x00000600, %rax	/* set OSFXSR, OSXMMEXCPT */
-	movq %rax, %cr4
-
-	/* Let's rock. */
-	call start_main
-
-	/* %rax has the return value - pass it on unmolested */
-_leave:
-	/* Restore old stack. */
-	pop %rsp
-
-	/* Return to the original context. */
-	ret

payloads/libpayload/arch/x86/libpayload.ldscript

@@ -26,13 +26,8 @@
  * SUCH DAMAGE.
  */
 
-#if CONFIG(LP_ARCH_X86_64)
-OUTPUT_FORMAT(elf64-x86-64)
-OUTPUT_ARCH(x86_64)
-#else
 OUTPUT_FORMAT(elf32-i386)
 OUTPUT_ARCH(i386)
-#endif
 
 ENTRY(_entry)
 

payloads/libpayload/arch/x86/multiboot_header.inc

@@ -1,54 +0,0 @@
-/*
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
- * Copyright (C) 2024 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#define MB_MAGIC 0x1BADB002
-#define MB_FLAGS 0x00010003
-
-	jmp _init
-
-/*
- * Note: The Multiboot standard requires Multiboot header to be placed
- * below 0x2000 in the resulting image.  See:
- * http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format.html
- */
-mb_header:
-	.long MB_MAGIC
-	.long MB_FLAGS
-	.long -(MB_MAGIC + MB_FLAGS)
-	.long mb_header
-	.long _start
-	.long _edata
-	.long _end
-	.long _init
-
-_init:
-	/* Store EAX and EBX */
-	movl %eax, loader_eax
-	movl %ebx, loader_ebx

payloads/libpayload/arch/x86/pt.S

@@ -1,149 +0,0 @@
-/*
- *
- * Copyright 2024 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * For reference see "AMD64 Architecture Programmer's Manual Volume 2",
- * Document 24593-Rev. 3.31-July 2019 Chapter 5.3.4
- *
- * Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty
- */
-
-.section .bss
-#define _PRES (1ULL << 0)
-#define _RW   (1ULL << 1)
-#define _US   (1ULL << 2)
-#define _A    (1ULL << 5)
-#define _D    (1ULL << 6)
-#define _PS   (1ULL << 7)
-
-.section .bss.pm4le
-.global pm4le
-.align 4096
-pm4le:
-.skip 8
-
-.section .bss.main_page_table
-.global main_page_table
-.align 4096
-main_page_table:
-.skip 8192
-
-.section .bss.extra_page_table
-.global extra_page_table
-.align 4096
-extra_page_table:
-.skip 32
-
-/*
- * WARNING: 32-bit/64-bit Mode Compatibility for Page Table Initialization
- * This `init_page_table` function is designed to work in both 32-bit protected
- * mode AND 64-bit long mode.
- *
- * Key Considerations:
- * - Assembly Instructions:  Use ONLY instructions that have the SAME binary representation
- *                           in both 32-bit and 64-bit modes.
- * - `.code64` Directive:  We're compiling with `.code64` to ensure the assembler uses
- *                         the correct 64-bit version of instructions (e.g., `inc`).
- * - Register Notation:
- *     - Use 64-bit register names (like `%rsi`) for register-indirect addressing to avoid
- *       incorrect address size prefixes.
- *     - It's safe to use `%esi` with `mov` instructions, as the high 32 bits are zeroed
- *       in 64-bit mode.
- *
- * IMPORTANT:
- * Thoroughly test ANY changes to this function in BOTH 32-bit and 64-bit boot environments.
- */
-
-.code64
-.section .text.init_page_table
-.globl init_page_table
-.type init_page_table, @function
-
-init_page_table:
-	mov $0x80000001, %eax
-	cpuid
-	test $(1 << 26), %edx
-	jnz setup_1gb
-
-setup_2mb:
-	mov $2048, %edi
-	mov $(_PRES + _RW + _US + _PS + _A + _D), %eax
-	mov $0, %ecx
-	mov $main_page_table, %esi
-
-loop_2mb:
-	mov %eax, (%rsi, %rcx, 8)
-	mov $0, 4(%rsi, %rcx, 8)
-	add $0x200000, %eax
-	inc %ecx
-	cmp %edi, %ecx
-	jb loop_2mb
-
-	mov $4, %edi
-	mov $main_page_table, %eax
-	add $(_PRES + _RW + _US + _A), %eax
-	mov $0, %ecx
-	mov $extra_page_table, %esi
-
-fill_extra_page_table:
-	mov %eax, (%rsi, %rcx, 8)
-	mov $0, 4(%rsi, %rcx, 8)
-	add $4096, %eax
-	inc %ecx
-	cmp %edi, %ecx
-	jb fill_extra_page_table
-
-	mov $extra_page_table, %eax
-	jmp leave
-
-setup_1gb:
-	mov $512, %edi
-	mov $(_PRES + _RW + _US + _PS + _A + _D), %eax
-	mov $0, %ebx
-	mov $0, %ecx
-	mov $main_page_table, %esi
-
-loop_1gb:
-	mov %eax, (%rsi, %rcx, 8)
-	mov %ebx, 4(%rsi, %rcx, 8)
-	add $0x40000000, %eax
-	cmp $0x40000000, %eax
-	ja no_overflow_1gb
-	inc %ebx
-no_overflow_1gb:
-	inc %ecx
-	cmp %edi, %ecx
-	jb loop_1gb
-
-	mov $main_page_table, %eax
-
-leave:
-	or $(_PRES + _RW + _US + _A), %eax
-	mov %eax, pm4le
-
-	ret

payloads/libpayload/arch/x86/string.c

@@ -81,16 +81,6 @@ void *memcpy(void *dest, const void *src, size_t n)
 {
 	unsigned long d0, d1, d2;
 
-#if CONFIG(LP_ARCH_X86_64)
-	asm volatile(
-		"rep ; movsq\n\t"
-		"mov %4,%%rcx\n\t"
-		"rep ; movsb\n\t"
-		: "=&c" (d0), "=&D" (d1), "=&S" (d2)
-		: "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src)
-		: "memory"
-	);
-#else
 	asm volatile(
 		"rep ; movsl\n\t"
 		"movl %4,%%ecx\n\t"
@@ -99,7 +89,6 @@ void *memcpy(void *dest, const void *src, size_t n)
 		: "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src)
 		: "memory"
 	);
-#endif
 
 	return dest;
 }

payloads/libpayload/bin/lpgcc

@@ -74,34 +74,34 @@ else
 fi
 
 if [ "$CONFIG_LP_ARCH_ARM" = "y" ]; then
-  _ARCHDIR=arm
+  _ARCHINCDIR=$_INCDIR/arm
+  _ARCHLIBDIR=$_LIBDIR/arm
   _ARCHEXTRA=""
-
+  _ARCH=arm
 fi
 if [ "$CONFIG_LP_ARCH_ARM64" = "y" ]; then
-  _ARCHDIR=arm64
+  _ARCHINCDIR=$_INCDIR/arm64
+  _ARCHLIBDIR=$_LIBDIR/arm64
   _ARCHEXTRA=""
+  _ARCH=arm64
 fi
 if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
-  _ARCHDIR=x86
-  if [ "$CONFIG_LP_ARCH_X86_32" = "y" ]; then
-    _ARCHEXTRA="-m32 "
-  else
-    _ARCHEXTRA="-m64 "
-  fi
+  _ARCHINCDIR=$_INCDIR/x86
+  _ARCHLIBDIR=$_LIBDIR/x86
+  _ARCHEXTRA="-m32 "
+  _ARCH=x86
 fi
 if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then
-  _ARCHDIR=mock
+  _ARCHINCDIR=$_INCDIR/mock
+  _ARCHLIBDIR=$_LIBDIR/mock
   _ARCHEXTRA=""
+  _ARCH=mock
 fi
 
-_ARCHINCDIR=$_INCDIR/$_ARCHDIR
-_ARCHLIBDIR=$_LIBDIR/$_ARCHDIR
-
 if [ -f $_LIBDIR/libpayload.ldscript ]; then
 	_LDDIR=$_LIBDIR
-elif [ -f $BASE/../arch/$_ARCHDIR/libpayload.ldscript ]; then
-	_LDDIR=$BASE/../arch/$_ARCHDIR
+elif [ -f $BASE/../arch/$_ARCH/libpayload.ldscript ]; then
+	_LDDIR=$BASE/../arch/$_ARCH
 fi
 # Host arch should youse default linker script
 if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then
@@ -126,10 +126,13 @@ CMDLINE=
 
 while [ $# -gt 0 ]; do
 	case $1 in
-	    -m32|-fno-stack-protector|-m64)
+	    -m32|-fno-stack-protector)
 		shift
 		continue
 		;;
+	    -m64)
+		error "Invalid option --64 - only 32 bit architectures are supported"
+		;;
 	    -c)
 		DOLINK=0
 		;;
@@ -202,6 +205,14 @@ if [ $DOLINK -eq 0 ]; then
     $DEFAULT_CC $CMDLINE $_CFLAGS
 else
     _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name`
+    if [ -f $_ARCHLIBDIR/head.o ]; then
+	    HEAD_O=$_ARCHLIBDIR/head.o
+    elif [ -f $_OBJ/head.o ]; then
+	    HEAD_O=$_OBJ/head.o
+    else
+	    echo "Could not find head.o"
+	    exit 1
+    fi
 
     if [ "$CONFIG_LP_ARM64_A53_ERRATUM_843419" = y ] &&
        grep -q fix-cortex-a53-843419 $_XCOMPILE; then
@@ -213,8 +224,13 @@ else
     _LDFLAGS="$_LDFLAGS -Wl,--defsym=CONFIG_LP_STACK_SIZE=$CONFIG_LP_STACK_SIZE"
 
     if [ $DEBUGME -eq 1 ]; then
-	echo "$DEFAULT_CC $_LDFLAGS $CMDLINE $_CFLAGS -lpayload $_LIBGCC"
+	echo "$DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC"
     fi
 
-    $DEFAULT_CC $_LDFLAGS $CMDLINE $_CFLAGS -lpayload -xnone $_LIBGCC
+    # Note: $_ARCHLIBDIR/head.o must be the first object being linked, because it
+    # contains a Multiboot header.  The Multiboot standard requires this
+    # header to be placed below 0x2000 in the resulting image.  See:
+    # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format.html
+
+    $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload -xnone $_LIBGCC
 fi

payloads/libpayload/drivers/storage/ahci_common.c

@@ -66,7 +66,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
 			    u8 *const user_buf, const size_t len,
 			    const int out)
 {
-	if ((uintptr_t)user_buf & 1) {
+	if ((u32)user_buf & 1) {
 		printf("ahci: Odd buffer pointer (%p).\n", user_buf);
 		if (dev->buf) /* orphaned buffer */
 			free(dev->buf - *(dev->buf - 1));
@@ -76,7 +76,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
 		dev->user_buf = user_buf;
 		dev->write_back = !out;
 		dev->buflen = len;
-		if ((uintptr_t)dev->buf & 1) {
+		if ((u32)dev->buf & 1) {
 			dev->buf[0] = 1;
 			dev->buf += 1;
 		} else {

payloads/libpayload/drivers/usb/uhci.c

@@ -274,7 +274,7 @@ uhci_stop(hci_t *controller)
 
 #define UHCI_SLEEP_TIME_US 30
 #define UHCI_TIMEOUT (USB_MAX_PROCESSING_TIME_US / UHCI_SLEEP_TIME_US)
-#define GET_TD(x) ((void *)(((unsigned long)(x))&~0xf))
+#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
 
 static td_t *
 wait_for_completed_qh(hci_t *controller, qh_t *qh)

payloads/libpayload/include/endian.h

@@ -96,16 +96,6 @@ static inline uint32_t be32dec(const void *pp)
 		(uint32_t)(p[2] << 8) | p[3]);
 }
 
-static inline uint64_t be64dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((uint64_t)p[0] << 56) | ((uint64_t)p[1] << 48) |
-		((uint64_t)p[2] << 40) | ((uint64_t)p[3] << 32) |
-		((uint64_t)p[4] << 24) | ((uint64_t)p[5] << 16) |
-		((uint64_t)p[6] <<  8) | p[7]);
-}
-
 static inline uint16_t le16dec(const void *pp)
 {
 	uint8_t const *p = (uint8_t const *)pp;
@@ -121,16 +111,6 @@ static inline uint32_t le32dec(const void *pp)
 		(uint32_t)(p[1] << 8) | p[0]);
 }
 
-static inline uint64_t le64dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((uint64_t)p[7] << 56) | ((uint64_t)p[6] << 48) |
-		((uint64_t)p[5] << 40) | ((uint64_t)p[4] << 32) |
-		((uint64_t)p[3] << 24) | ((uint64_t)p[2] << 16) |
-		((uint64_t)p[1] <<  8) | p[0]);
-}
-
 static inline void bebitenc(void *pp, uint32_t u, uint8_t b)
 {
 	uint8_t *p = (uint8_t *)pp;
@@ -150,11 +130,6 @@ static inline void be32enc(void *pp, uint32_t u)
 	bebitenc(pp, u, 4);
 }
 
-static inline void be64enc(void *pp, uint32_t u)
-{
-	bebitenc(pp, u, 8);
-}
-
 static inline void lebitenc(void *pp, uint32_t u, uint8_t b)
 {
 	uint8_t *p = (uint8_t *)pp;
@@ -174,11 +149,6 @@ static inline void le32enc(void *pp, uint32_t u)
 	lebitenc(pp, u, 4);
 }
 
-static inline void le64enc(void *pp, uint32_t u)
-{
-	lebitenc(pp, u, 8);
-}
-
 /* Deprecated names (not in glibc / BSD) */
 #define htobew(in) htobe16(in)
 #define htobel(in) htobe32(in)

payloads/libpayload/include/stdint.h

@@ -54,12 +54,4 @@ typedef long ptrdiff_t;
 #define UINT32_MAX	(4294967295U)
 #define UINT64_MAX	(18446744073709551615ULL)
 
-#ifndef SIZE_MAX
-#ifdef __SIZE_MAX__
-#define SIZE_MAX __SIZE_MAX__
-#else
-#define SIZE_MAX (~(size_t)0)
-#endif /* __SIZE_MAX__ */
-#endif /* SIZE_MAX */
-
 #endif

payloads/libpayload/include/string.h

@@ -29,7 +29,6 @@
 #ifndef _STRING_H
 #define _STRING_H
 
-#include <commonlib/bsd/string.h>
 #include <stddef.h>
 
 /**
@@ -47,12 +46,16 @@ int memcmp(const void *s1, const void *s2, size_t len);
  * @defgroup string String functions
  * @{
  */
+size_t strnlen(const char *str, size_t maxlen);
+size_t strlen(const char *str);
 int strcmp(const char *s1, const char *s2);
 int strncmp(const char *s1, const char *s2, size_t maxlen);
 int strcasecmp(const char *s1, const char *s2);
 int strncasecmp(const char *s1, const char *s2, size_t maxlen);
 char *strncpy(char *d, const char *s, size_t n);
 char *strcpy(char *d, const char *s);
+char *strncat(char *d, const char *s, size_t n);
+char *strcat(char *d, const char *s);
 char *strchr(const char *s, int c);
 char *strrchr(const char *s, int c);
 char *strdup(const char *s);

payloads/libpayload/include/sysinfo.h

@@ -114,8 +114,6 @@ struct sysinfo_t {
 	uintptr_t acpi_cnvs;
 	uintptr_t acpi_rsdp;
 	uintptr_t smbios;
-	uintptr_t cse_bp_info;
-	uintptr_t cse_info;
 
 #define UNDEFINED_STRAPPING_ID	(~0)
 #define UNDEFINED_FW_CONFIG	~((uint64_t)0)

payloads/libpayload/include/x86/arch/exception.h

@@ -29,7 +29,6 @@
 #ifndef _ARCH_EXCEPTION_H
 #define _ARCH_EXCEPTION_H
 
-#include <stddef.h>
 #include <stdint.h>
 
 void exception_init_asm(void);
@@ -39,28 +38,20 @@ void disable_interrupts(void);
 /** Returns 1 if interrupts are enabled. */
 int interrupts_enabled(void);
 
-#if CONFIG(LP_ARCH_X86_64)
-struct exception_state {
+struct exception_state
+{
 	/* Careful: x86/gdb.c currently relies on the size and order of regs. */
 	struct {
-		size_t reg_ax;
-		size_t reg_bx;
-		size_t reg_cx;
-		size_t reg_dx;
-		size_t reg_si;
-		size_t reg_di;
-		size_t reg_bp;
-		size_t reg_sp;
-		size_t reg_r8;
-		size_t reg_r9;
-		size_t reg_r10;
-		size_t reg_r11;
-		size_t reg_r12;
-		size_t reg_r13;
-		size_t reg_r14;
-		size_t reg_r15;
-		size_t reg_ip;
-		size_t reg_flags;
+		u32 eax;
+		u32 ecx;
+		u32 edx;
+		u32 ebx;
+		u32 esp;
+		u32 ebp;
+		u32 esi;
+		u32 edi;
+		u32 eip;
+		u32 eflags;
 		u32 cs;
 		u32 ss;
 		u32 ds;
@@ -68,39 +59,13 @@ struct exception_state {
 		u32 fs;
 		u32 gs;
 	} regs;
-	size_t error_code;
-	size_t vector;
+	u32 error_code;
+	u32 vector;
 } __packed;
-#else
-struct exception_state {
-	/* Careful: x86/gdb.c currently relies on the size and order of regs. */
-	struct {
-		size_t reg_ax;
-		size_t reg_cx;
-		size_t reg_dx;
-		size_t reg_bx;
-		size_t reg_sp;
-		size_t reg_bp;
-		size_t reg_si;
-		size_t reg_di;
-		size_t reg_ip;
-		size_t reg_flags;
-		u32 cs;
-		u32 ss;
-		u32 ds;
-		u32 es;
-		u32 fs;
-		u32 gs;
-	} regs;
-	size_t error_code;
-	size_t vector;
-} __packed;
-#endif
-
 extern struct exception_state *exception_state;
 
-extern u8 exception_stack[];
-extern u8 *exception_stack_end;
+extern u32 exception_stack[];
+extern u32 *exception_stack_end;
 
 enum {
 	EXC_DE = 0, /* Divide by zero */

payloads/libpayload/include/x86/arch/rdtsc.h

@@ -33,9 +33,9 @@
 
 static u64 rdtsc(void)
 {
-	u32 lo, hi;
-	__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
-	return (u64)hi << 32 | lo;
+	u64 val;
+	__asm__ __volatile__ ("rdtsc" : "=A" (val));
+	return val;
 }
 
 #endif

payloads/libpayload/libc/Makefile.mk

@@ -29,7 +29,7 @@
 
 libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c
 libc-$(CONFIG_LP_LIBC) += memory.c ctype.c lib.c libgcc.c
-libc-$(CONFIG_LP_LIBC) += rand.c time.c
+libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c
 libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c
 libc-$(CONFIG_LP_LIBC) += args.c
 libc-$(CONFIG_LP_LIBC) += strlcpy.c
@@ -47,9 +47,7 @@ ifeq ($(CONFIG_LP_LIBC),y)
 libc-srcs += $(coreboottop)/src/commonlib/bsd/elog.c
 libc-srcs += $(coreboottop)/src/commonlib/bsd/gcd.c
 libc-srcs += $(coreboottop)/src/commonlib/bsd/ipchksum.c
-libc-srcs += $(coreboottop)/src/commonlib/bsd/string.c
 ifeq ($(CONFIG_LP_GPL),y)
-libc-srcs += $(coreboottop)/src/commonlib/device_tree.c
 libc-srcs += $(coreboottop)/src/commonlib/list.c
 endif
 endif

payloads/libpayload/libc/coreboot.c

@@ -262,12 +262,6 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
 	case CBMEM_ID_MEM_CHIP_INFO:
 		info->mem_chip_base = cbmem_entry->address;
 		break;
-	case CBMEM_ID_CSE_BP_INFO:
-		info->cse_bp_info = cbmem_entry->address;
-		break;
-	case CBMEM_ID_CSE_INFO:
-		info->cse_info = cbmem_entry->address;
-		break;
 	default:
 		break;
 	}

payloads/libpayload/libc/exec.c

@@ -29,10 +29,8 @@
 #include <libpayload-config.h>
 #include <libpayload.h>
 
-#if CONFIG(LP_ARCH_X86_32)
+#if CONFIG(LP_ARCH_X86)
 extern void i386_do_exec(long addr, int argc, char **argv, int *ret);
-#else
-#error "exec does not currently support x86_64."
 #endif
 
 /**
@@ -47,7 +45,7 @@ int exec(long addr, int argc, char **argv)
 {
 	int val = -1;
 
-#if CONFIG(LP_ARCH_X86_32)
+#if CONFIG(LP_ARCH_X86)
 	i386_do_exec(addr, argc, argv, &val);
 #endif
 	return val;

payloads/libpayload/libc/string.c

@@ -35,6 +35,50 @@
 #include <limits.h>
 #include <errno.h>
 
+/**
+ * Calculate the length of a fixed-size string.
+ *
+ * @param str The input string.
+ * @param maxlen Return at most maxlen characters as length of the string.
+ * @return The length of the string, not including the final NUL character.
+ * 	   The maximum length returned is maxlen.
+ */
+size_t strnlen(const char *str, size_t maxlen)
+{
+	size_t len = 0;
+
+	/* NULL and empty strings have length 0. */
+	if (!str)
+		return 0;
+
+	/* Loop until we find a NUL character, or maxlen is reached. */
+	while ((*str++ != '\0') && (len < maxlen))
+		len++;
+
+	return len;
+}
+
+/**
+ * Calculate the length of a string.
+ *
+ * @param str The input string.
+ * @return The length of the string, not including the final NUL character.
+ */
+size_t strlen(const char *str)
+{
+	size_t len = 0;
+
+	/* NULL and empty strings have length 0. */
+	if (!str)
+		return 0;
+
+	/* Loop until we find a NUL character. */
+	while (*str++ != '\0')
+		len++;
+
+	return len;
+}
+
 /**
  * Compare two strings.
  *
@@ -152,6 +196,46 @@ char *strcpy(char *d, const char *s)
 	return strncpy(d, s, strlen(s) + 1);
 }
 
+/**
+ * Concatenates two strings
+ *
+ * @param d The destination string.
+ * @param s The source string.
+ * @return A pointer to the destination string.
+ */
+char *strcat(char *d, const char *s)
+{
+	char *p = d + strlen(d);
+	size_t sl = strlen(s);
+
+	for (size_t i = 0; i < sl; i++)
+		p[i] = s[i];
+
+	p[sl] = '\0';
+	return d;
+}
+
+/**
+ * Concatenates two strings with a maximum length.
+ *
+ * @param d The destination string.
+ * @param s The source string.
+ * @param n Not more than n characters from s will be appended to d.
+ * @return A pointer to the destination string.
+ */
+char *strncat(char *d, const char *s, size_t n)
+{
+	char *p = d + strlen(d);
+	size_t sl = strlen(s);
+	size_t max = n > sl ? sl : n;
+
+	for (size_t i = 0; i < max; i++)
+		p[i] = s[i];
+
+	p[max] = '\0';
+	return d;
+}
+
 /**
  * Concatenates two strings with a maximum length.
  *

payloads/libpayload/vboot/Makefile.mk

@@ -15,8 +15,7 @@ vboot-fixup-includes = $(filter -I$(coreboottop)/%, $(1)) \
 		       $(filter-out -I$(coreboottop)/%,$(1)))))
 
 VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM) := arm
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86_32) := x86
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86_64) := x86_64
+VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86) := x86
 VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
 
 ifneq ($(CONFIG_LP_ARCH_MOCK),)

spd/lp4x/memory_parts.json

@@ -399,18 +399,6 @@
                 "ranksPerChannel": 1,
                 "speedMbps": 4267
             }
-	},
-	{
-            "name": "SDVB8D8A34XGCL3N3T",
-            "attribs": {
-                "densityPerChannelGb": 8,
-                "banks": 8,
-                "channelsPerDie": 2,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 4267
-            }
 	}
     ]
 }

spd/lp4x/set-0/parts_spd_manifest.generated.txt

@@ -34,4 +34,3 @@ H54G68CYRBX248,spd-2.hex
 K4UCE3Q4AB-MGCL,spd-2.hex
 CXDB4ABAM-ML,spd-8.hex
 CXDB4CBAM-ML-A,spd-8.hex
-SDVB8D8A34XGCL3N3T,spd-1.hex

spd/lp4x/set-1/parts_spd_manifest.generated.txt

@@ -34,4 +34,3 @@ H54G68CYRBX248,spd-2.hex
 K4UCE3Q4AB-MGCL,spd-2.hex
 CXDB4ABAM-ML,spd-11.hex
 CXDB4CBAM-ML-A,spd-11.hex
-SDVB8D8A34XGCL3N3T,spd-5.hex

spd/lp5/memory_parts.json

@@ -240,28 +240,6 @@
                 "speedMbps": 8533,
                 "lp5x": true
             }
-        },
-        {
-            "name":  "MT62F1G32D2DS-023 WT:C",
-            "attribs": {
-                "densityPerDieGb": 16,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 8533,
-                "lp5x": true
-            }
-        },
-        {
-            "name":  "K3KL8L80DM-MGCU",
-            "attribs": {
-                "densityPerDieGb": 16,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 8533,
-                "lp5x": true
-            }
         }
     ]
 }