mb/system76: Use default GMA brightness levels

This reverts commit 1f81af52a4 ("mb/system76: Add custom backlight
levels for Intel GMA").

Defaulting to 40% can make the screen hard to read as System76's
firmware setup uses white text on a gray background.

Change-Id: I13ab3797319c4db6e800737a3f4e4344e3b588f3
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/arch/x86/cpu_common.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <commonlib/helpers.h>
 #include <cpu/cpu.h>
 #include <types.h>
 
@@ -235,18 +234,3 @@ bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
 
 	return true;
 }
-
-bool is_cache_sets_power_of_two(void)
-{
-	struct cpu_cache_info info;
-
-	if (!fill_cpu_cache_info(CACHE_L3, &info))
-		return false;
-
-	size_t cache_sets = cpu_get_cache_sets(&info);
-
-	if (IS_POWER_OF_2(cache_sets))
-		return true;
-
-	return false;
-}

src/arch/x86/include/arch/cpu.h

@@ -329,15 +329,6 @@ uint8_t cpu_get_c_substate_support(const int state);
  */
 bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);
 
-/*
- * Determines whether the number of cache sets is a power of two.
- *
- * Cache designs often favor power-of-two set counts for efficient indexing
- * and addressing. This function checks if the provided cache configuration
- * adheres to this practice.
- */
-bool is_cache_sets_power_of_two(void);
-
 #if CONFIG(RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT)
 unsigned int get_reserved_phys_addr_bits(void);
 #else

src/cpu/intel/microcode/microcode.c

@@ -241,12 +241,6 @@ const void *intel_microcode_find(void)
 	static bool microcode_checked;
 	static const void *ucode_update;
 
-	if (ENV_CACHE_AS_RAM) {
-		printk(BIOS_ERR, "Microcode Error: Early microcode patching is not supported due"
-				"to NEM limitation\n");
-		return NULL;
-	}
-
 	if (microcode_checked)
 		return ucode_update;
 

src/cpu/x86/mtrr/earlymtrr.c

@@ -37,9 +37,6 @@ void set_var_mtrr(
 	/* FIXME: It only support 4G less range */
 	msr_t basem, maskm;
 
-	if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM)
-		printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n",
-			 type);
 	if (!IS_POWER_OF_2(size))
 		printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
 	if (size < 4 * KiB)

src/drivers/i2c/tas5825m/tas5825m.c

@@ -1,24 +1,23 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <device/i2c_bus.h>
+#include <device/smbus.h>
+#include <device/pci.h>
 #include "chip.h"
 #include "tas5825m.h"
 
 int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value)
 {
-	return i2c_dev_writeb_at(dev, addr, value);
+	return smbus_write_byte(dev, addr, value);
 }
 
+//TODO: use I2C block write for better performance
 int tas5825m_write_block_at(struct device *dev, uint8_t addr,
 	const uint8_t *values, uint8_t length)
 {
-	// TODO: use I2C block write for better performance; SMBus does not
-	// have `transfer` op for it.
-
 	int res = 0;
 	for (uint8_t i = 0; i < length; i++) {
-		res = i2c_dev_writeb_at(dev, addr + i, values[i]);
+		res = smbus_write_byte(dev, addr + i, values[i]);
 		if (res < 0)
 			return res;
 	}
@@ -46,7 +45,8 @@ __weak int tas5825m_setup(struct device *dev, int id)
 
 static void tas5825m_init(struct device *dev)
 {
-	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && i2c_link(dev)) {
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C &&
+		ops_smbus_bus(get_pbus_smbus(dev))) {
 		printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev));
 
 		struct drivers_i2c_tas5825m_config *config = dev->chip_info;

src/drivers/mrc_cache/Kconfig

@@ -56,12 +56,14 @@ config MRC_SAVE_HASH_IN_TPM
 
 config MRC_CACHE_USING_MRC_VERSION
 	bool
+	default y if UDK_VERSION >= 202302
 	default n
 	help
 	  Use the MRC version info from FSP extended header to store the MRC cache data.
 	  This method relies on the FSP_PRODUCER_DATA_TABLES belongs to the
 	  `FspProducerDataHeader.h`file to get the MRC version.
 
-	  Supported platform can retrieve the MRC version by directly parsing the binary.
+	  Intel FSP built with EDK2 version 202302 onwards has support to retrieve the
+	  MRC version by directly parsing the binary.
 
 endif # CACHE_MRC_SETTINGS

src/ec/system76/ec/Makefile.mk

@@ -5,7 +5,6 @@ all-y += system76_ec.c
 
 ramstage-y += smbios.c
 ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c
-ramstage-y += usbc_mux.c
 
 smm-$(CONFIG_DEBUG_SMI) += system76_ec.c
 

src/ec/system76/ec/usbc_mux.c

@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include "system76_ec.h"
-#include <console/console.h>
-#include <delay.h>
-#include <device/usbc_mux.h>
-#include <timer.h>
-#include <types.h>
-
-#define CMD_USBC_MUX_INFO 23
-
-enum usbc_mux_flags {
-	USBC_MUX_DP = BIT(0),
-	USBC_MUX_USB = BIT(1),
-	USBC_MUX_CABLE = BIT(2),
-	USBC_MUX_POLARITY = BIT(3),
-	USBC_MUX_HPD_LVL = BIT(4),
-	USBC_MUX_HPD_IRQ = BIT(5),
-	USBC_MUX_UFP = BIT(6),
-	USBC_MUX_DBG_ACC = BIT(7),
-};
-
-static int system76_ec_get_mux_info(int port, struct usbc_mux_info *info)
-{
-	uint8_t request[1] = { port };
-	uint8_t reply[3] = { 0 };
-	uint8_t flags;
-	uint8_t pin_mode;
-	bool res;
-
-	if (!info)
-		return -1;
-
-	res = system76_ec_cmd(CMD_USBC_MUX_INFO, request, ARRAY_SIZE(request),
-			reply, ARRAY_SIZE(reply));
-	if (!res)
-		return -1;
-
-	flags = reply[1];
-	pin_mode = reply[2];
-
-	info->dp = !!(flags & USBC_MUX_DP);
-	info->usb = !!(flags & USBC_MUX_USB);
-	info->cable = !!(flags & USBC_MUX_CABLE);
-	info->polarity = !!(flags & USBC_MUX_POLARITY);
-	info->hpd_lvl = !!(flags & USBC_MUX_HPD_LVL);
-	info->hpd_irq = !!(flags & USBC_MUX_HPD_IRQ);
-	info->ufp = !!(flags & USBC_MUX_UFP);
-	info->dbg_acc = !!(flags & USBC_MUX_DBG_ACC);
-	info->dp_pin_mode = pin_mode;
-
-	printk(BIOS_SPEW, "%s: dp=%u, usb=%u\n", __func__, info->dp, info->usb);
-	printk(BIOS_SPEW, "%s: cable=%u, polarity=%u\n", __func__, info->cable, info->polarity);
-	printk(BIOS_SPEW, "%s: hpd_lvl=%u, hpd_irq=%u\n", __func__, info->hpd_lvl, info->hpd_irq);
-	printk(BIOS_SPEW, "%s: ufp=%u, dbg_acc=%u\n", __func__, info->ufp, info->dbg_acc);
-	printk(BIOS_SPEW, "%s: pin_mode=0x%x\n", __func__, info->dp_pin_mode);
-
-	return 0;
-}
-
-static int system76_ec_wait_for_connection(long timeout_ms)
-{
-	// TODO
-	return 1;
-}
-
-static int system76_ec_enter_dp_mode(int port)
-{
-	// TODO
-	return 0;
-}
-
-static int system76_ec_wait_for_dp_mode_entry(int port, long timeout_ms)
-{
-	struct usbc_mux_info info;
-
-	if (system76_ec_get_mux_info(port, &info) < 0) {
-		printk(BIOS_WARNING, "%s: could not get usbc mux info\n", __func__);
-		return -1;
-	}
-
-	if (!info.dp) {
-		printk(BIOS_WARNING, "DP mode not ready\n");
-		return -1;
-	}
-
-	return 0;
-}
-
-static int system76_ec_wait_for_hpd(int port, long timeout_ms)
-{
-	struct usbc_mux_info info;
-	struct stopwatch sw;
-
-	stopwatch_init_msecs_expire(&sw, timeout_ms);
-	while (1) {
-		if (system76_ec_get_mux_info(port, &info) < 0) {
-			printk(BIOS_WARNING, "%s: could not get usbc mux info\n", __func__);
-			return -1;
-		}
-
-		if (info.hpd_lvl)
-			break;
-
-		if (stopwatch_expired(&sw)) {
-			printk(BIOS_WARNING, "HPD not ready after %ldms\n", timeout_ms);
-			return -1;
-		}
-
-		mdelay(100);
-	}
-
-	printk(BIOS_INFO, "HPD ready after %lldms\n", stopwatch_duration_msecs(&sw));
-	return 0;
-}
-
-static const struct usbc_ops system76_ec_usbc_ops = {
-	.mux_ops = {
-		.get_mux_info = system76_ec_get_mux_info,
-	},
-	.dp_ops = {
-		.wait_for_connection = system76_ec_wait_for_connection,
-		.enter_dp_mode = system76_ec_enter_dp_mode,
-		.wait_for_dp_mode_entry = system76_ec_wait_for_dp_mode_entry,
-		.wait_for_hpd = system76_ec_wait_for_hpd,
-	},
-};
-
-const struct usbc_ops *usbc_get_ops(void)
-{
-	return &system76_ec_usbc_ops;
-}

src/include/device/pci_ids.h

@@ -4128,7 +4128,6 @@
 #define PCI_DID_INTEL_MTL_P_GT2_2			0x7d50
 #define PCI_DID_INTEL_MTL_P_GT2_3			0x7d55
 #define PCI_DID_INTEL_MTL_P_GT2_4			0x7d60
-#define PCI_DID_INTEL_MTL_P_GT2_5			0x7dd5
 #define PCI_DID_INTEL_RPL_HX_GT1			0xa788
 #define PCI_DID_INTEL_RPL_HX_GT2			0xa78b
 #define PCI_DID_INTEL_RPL_HX_GT3			0x4688

src/include/device/usbc_mux.h

@@ -3,9 +3,6 @@
 #ifndef __USBC_MUX_H__
 #define __USBC_MUX_H__
 
-#include <stdbool.h>
-#include <stdint.h>
-
 /* struct to hold all USB-C mux related variables */
 struct usbc_mux_info {
 	bool dp; /* DP connected */

src/include/spd_bin.h

@@ -36,7 +36,7 @@
 #define DDR4_SPD_PART_LEN	20
 #define DDR4_SPD_SN_OFF		325
 #define MAX_SPD_PAGE_SIZE_SPD5	128
-#define MAX_SPD_SIZE		(SPD_PAGE_LEN * 4)
+#define MAX_SPD_SIZE		(SPD_PAGE_LEN * SPD_SN_LEN)
 #define SPD_HUB_MEMREG(addr)	((u8)(0x80 | (addr)))
 #define SPD5_MR11		0x0B
 #define SPD5_MR0		0x00

src/lib/spd_cache.c

@@ -209,9 +209,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
 
 	dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
 
-	if (dram_type == SPD_DRAM_DDR5)
+	if (dram_type == SPD_DRAM_DDR4 || dram_type == SPD_DRAM_DDR5)
-		blk->len = CONFIG_DIMM_SPD_SIZE;
-	else if (dram_type == SPD_DRAM_DDR4)
 		blk->len = SPD_PAGE_LEN_DDR4;
 	else
 		blk->len = SPD_PAGE_LEN;

src/mainboard/google/rex/Kconfig

@@ -58,6 +58,7 @@ config BOARD_GOOGLE_BASEBOARD_REX
 	select HAVE_SLP_S0_GATE
 	select MAINBOARD_HAS_CHROMEOS
 	select MEMORY_SOLDERDOWN
+	select SOC_INTEL_COMMON_BASECODE_RAMTOP
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SOC_INTEL_IOE_DIE_SUPPORT
 	select SOC_INTEL_METEORLAKE_U_H

src/mainboard/intel/mtlrvp/Kconfig

@@ -19,6 +19,7 @@ config BOARD_INTEL_MTLRVP_COMMON
 	select HAVE_ACPI_TABLES
 	select HAVE_SPD_IN_CBFS
 	select MAINBOARD_HAS_CHROMEOS
+	select SOC_INTEL_COMMON_BASECODE_RAMTOP
 	select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
 	select SOC_INTEL_CSE_LITE_SKU
 	select SOC_INTEL_METEORLAKE_U_H

src/mainboard/system76/addw1/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/adl/Kconfig

@@ -11,8 +11,6 @@ config BOARD_SYSTEM76_ADL_COMMON
 	select DRIVERS_INTEL_USB4_RETIMER
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_LOCKDOWN
-	select ENABLE_TCSS_DISPLAY_DETECTION
-	select ENABLE_TCSS_USB_DETECTION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT

src/mainboard/system76/adl/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/adl/acpi/mainboard.asl

@@ -11,8 +11,6 @@
 Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
-		#include "backlight.asl"
-
 #if CONFIG(DRIVERS_GFX_NVIDIA)
 		Scope (PEG2) {
 			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>

src/mainboard/system76/adl/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/adl/dsdt.asl

@@ -20,6 +20,7 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/alderlake/acpi/southbridge.asl>
 		#include <soc/intel/alderlake/acpi/tcss.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/bonw14/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/cml-u/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/cml-u/acpi/mainboard.asl

@@ -6,9 +6,6 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
-	Scope (PCI0) {
-		#include "backlight.asl"
-	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/cml-u/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/cml-u/dsdt.asl

@@ -19,6 +19,7 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/gaze15/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -9,7 +9,6 @@
 Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
-		#include "backlight.asl"
 		Device (PEGP) {
 			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
 			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>

src/mainboard/system76/gaze15/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/gaze15/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 	Device (\_SB.PCI0) {
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/kbl-u/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/kbl-u/acpi/mainboard.asl

@@ -1,10 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 Scope (\_SB) {
-	Scope (PCI0) {
-		#include "backlight.asl"
-	}
-
 	#include "ac.asl"
 	#include "battery.asl"
 	#include "buttons.asl"

src/mainboard/system76/kbl-u/cmos.layout

@@ -12,10 +12,7 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -35,4 +32,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/kbl-u/dsdt.asl

@@ -19,6 +19,7 @@ DefinitionBlock(
 	{
 		#include <soc/intel/skylake/acpi/systemagent.asl>
 		#include <soc/intel/skylake/acpi/pch.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/mtl/Kconfig

@@ -1,117 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-config BOARD_SYSTEM76_MTL_COMMON
-	def_bool n
-	select BOARD_ROMSIZE_KB_32768
-	select DRIVERS_GENERIC_BAYHUB_LV2
-	select DRIVERS_GENERIC_CBFS_SERIAL
-	select DRIVERS_GENERIC_CBFS_UUID
-	select DRIVERS_I2C_HID
-	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_LOCKDOWN
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
-	select HAVE_OPTION_TABLE
-	select INTEL_GMA_HAVE_VBT
-	select INTEL_LPSS_UART_FOR_CONSOLE
-	select MAINBOARD_HAS_TPM2
-	select MEMORY_MAPPED_TPM
-	select NO_UART_ON_SUPERIO
-	select PCIEXP_SUPPORT_RESIZABLE_BARS
-	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_CRASHLOG
-	select SOC_INTEL_METEORLAKE
-	select SPD_READ_BY_WORD
-	select SYSTEM_TYPE_LAPTOP
-	select TPM_RDRESP_NEED_DELAY
-
-config BOARD_SYSTEM76_DARP10
-	select BOARD_SYSTEM76_MTL_COMMON
-	select MAINBOARD_USES_IFD_GBE_REGION
-	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-	select SOC_INTEL_METEORLAKE_U_H
-
-config BOARD_SYSTEM76_DARP10_B
-	select BOARD_SYSTEM76_MTL_COMMON
-	select MAINBOARD_USES_IFD_GBE_REGION
-	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-	select SOC_INTEL_METEORLAKE_U_H
-
-config BOARD_SYSTEM76_LEMP13
-	select BOARD_SYSTEM76_MTL_COMMON
-	select DRIVERS_I2C_TAS5825M
-	select HAVE_SPD_IN_CBFS
-	select SOC_INTEL_METEORLAKE_U_H
-	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-
-config BOARD_SYSTEM76_LEMP13_B
-	select BOARD_SYSTEM76_MTL_COMMON
-	select DRIVERS_I2C_TAS5825M
-	select HAVE_SPD_IN_CBFS
-	select SOC_INTEL_METEORLAKE_U_H
-	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-
-if BOARD_SYSTEM76_MTL_COMMON
-
-config MAINBOARD_DIR
-	default "system76/mtl"
-
-config VARIANT_DIR
-	default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
-	default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
-
-config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
-config MAINBOARD_PART_NUMBER
-	default "darp10" if BOARD_SYSTEM76_DARP10
-	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
-	default "lemp13" if BOARD_SYSTEM76_LEMP13
-	default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
-
-config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B
-	default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B
-
-config MAINBOARD_VERSION
-	default "darp10" if BOARD_SYSTEM76_DARP10
-	default "darp10-b" if BOARD_SYSTEM76_DARP10_B
-	default "lemp13" if BOARD_SYSTEM76_LEMP13
-	default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B
-
-config CMOS_DEFAULT_FILE
-	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
-
-config CONSOLE_POST
-	default y
-
-config D3COLD_SUPPORT
-	default n
-
-config DIMM_SPD_SIZE
-	default 1024
-
-config FMDFILE
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
-
-config ONBOARD_VGA_IS_PRIMARY
-	default y
-
-config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
-	default 36
-
-config POST_DEVICE
-	default n
-
-config TPM_MEASURED_BOOT
-	default y
-
-config UART_FOR_CONSOLE
-	default 0
-
-# PM Timer Disabled, saves power
-config USE_PM_ACPI_TIMER
-	default n
-
-endif

src/mainboard/system76/mtl/Kconfig.name

@@ -1,13 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-config BOARD_SYSTEM76_DARP10
-	bool "darp10"
-
-config BOARD_SYSTEM76_DARP10_B
-	bool "darp10-b"
-
-config BOARD_SYSTEM76_LEMP13
-	bool "lemp13"
-
-config BOARD_SYSTEM76_LEMP13_B
-	bool "lemp13-b"

src/mainboard/system76/mtl/Makefile.mk

@@ -1,20 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
-
-ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
-endif
-
-bootblock-y += bootblock.c
-bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
-
-romstage-y += variants/$(VARIANT_DIR)/romstage.c
-
-ramstage-y += ramstage.c
-ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-ramstage-y += variants/$(VARIANT_DIR)/gpio.c
-ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
-ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
-
-SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD

src/mainboard/system76/mtl/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		100, /* default AC */
-		100, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/mtl/acpi/mainboard.asl

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define EC_GPE_SCI 0x6E
-#define EC_GPE_SWI 0x6B
-#include <ec/system76/ec/acpi/ec.asl>
-
-Scope (\_SB) {
-	#include "sleep.asl"
-	Scope (PCI0) {
-		#include "backlight.asl"
-	}
-}

src/mainboard/system76/mtl/acpi/sleep.asl

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-External(\TBTS, MethodObj)
-
-Method(MPTS, 1, Serialized) {
-	If (CondRefOf(\TBTS)) {
-		\TBTS()
-	}
-}

src/mainboard/system76/mtl/board_info.txt

@@ -1,6 +0,0 @@
-Vendor name: System76
-Category: laptop
-ROM package: WSON-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y

src/mainboard/system76/mtl/bootblock.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <mainboard/gpio.h>
-
-void bootblock_mainboard_early_init(void)
-{
-	mainboard_configure_early_gpios();
-}

src/mainboard/system76/mtl/cmos.default

@@ -1,5 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-boot_option=Fallback
-debug_level=Debug
-me_state=Disable

src/mainboard/system76/mtl/cmos.layout

@@ -1,43 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-entries
-
-0	384	r	0	reserved_memory
-
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-
-# RTC_CLK_ALTCENTURY
-400	8	r	0	century
-
-412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
-
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
-984	16	h	0	check_sum
-
-enumerations
-
-2	0	Enable
-2	1	Disable
-
-4	0	Fallback
-4	1	Normal
-
-6	0	Emergency
-6	1	Alert
-6	2	Critical
-6	3	Error
-6	4	Warning
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 408 799 984

src/mainboard/system76/mtl/devicetree.cb

@@ -1,65 +0,0 @@
-chip soc/intel/meteorlake
-	register "common_soc_config" = "{
-		// Touchpad I2C bus
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 80,
-			.fall_time_ns = 110,
-		},
-	}"
-
-	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
-
-	# Thermal
-	register "tcc_offset" = "8"
-
-	device cpu_cluster 0 on end
-
-	device domain 0 on
-		device ref system_agent on end
-		device ref igpu on
-			# DDIA is eDP, TCP2 is HDMI
-			register "ddi_port_A_config" = "1"
-			register "ddi_ports_config" = "{
-				[DDI_PORT_A] = DDI_ENABLE_HPD,
-				[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
-			}"
-
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
-		device ref ioe_shared_sram on end
-		device ref pmc_shared_sram on end
-		device ref cnvi_wifi on
-			register "cnvi_bt_core" = "true"
-			register "cnvi_bt_audio_offload" = "true"
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end
-		device ref i2c1 on
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
-		end
-
-		device ref heci1 on end
-		device ref soc_espi on
-			register "gen1_dec" = "0x00040069" # EC PM channel
-			register "gen2_dec" = "0x00fc0e01" # AP/EC command
-			register "gen3_dec" = "0x00fc0f01" # AP/EC debug
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end
-		device ref p2sb on end
-		device ref hda on
-			register "pch_hda_sdi_enable[0]" = "1"
-			register "pch_hda_audio_link_hda_enable" = "1"
-			register "pch_hda_idisp_codec_enable" = "1"
-			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
-			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
-		end
-		device ref smbus on end
-		device ref fast_spi on end
-	end
-end

src/mainboard/system76/mtl/dsdt.asl

@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS
-#include <soc/gpio.h>
-
-#include <acpi/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725
-)
-{
-	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/common/block/acpi/acpi/platform.asl>
-	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Device (\_SB.PCI0)
-	{
-		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
-		#include <soc/intel/meteorlake/acpi/southbridge.asl>
-		#include <soc/intel/meteorlake/acpi/tcss.asl>
-	}
-
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-	Scope (\_SB.PCI0.LPCB)
-	{
-		#include <drivers/pc80/pc/ps2_controller.asl>
-	}
-
-	#include "acpi/mainboard.asl"
-}

src/mainboard/system76/mtl/include/mainboard/gpio.h

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef MAINBOARD_GPIO_H
-#define MAINBOARD_GPIO_H
-
-void mainboard_configure_early_gpios(void);
-void mainboard_configure_gpios(void);
-
-#endif

src/mainboard/system76/mtl/ramstage.c

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mainboard/gpio.h>
-#include <soc/ramstage.h>
-
-static void mainboard_init(void *chip_info)
-{
-	mainboard_configure_gpios();
-}
-
-struct chip_operations mainboard_ops = {
-	.init = mainboard_init,
-};

src/mainboard/system76/mtl/spd/samsung-M425R1GB4BB0-CQKOD.spd.hex

@@ -1,65 +0,0 @@
-# Samsung M425R1GB4BB0-CQKOD
-30 10 12 03 04 00 40 42 00 00 00 00 90 02 00 00
-00 00 00 00 A0 01 F2 03 7A 0D 00 00 00 00 80 3E
-80 3E 80 3E 00 7D 80 BB 30 75 27 01 A0 00 82 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 88 13 08 88 13 08 20 4E 20 10
-27 10 1A 41 28 10 27 10 C4 09 04 4C 1D 0C 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-10 00 80 B3 80 21 80 B3 82 20 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 0F 01 02 81 00 22 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 D1
-80 CE 00 00 00 00 00 00 00 4D 34 32 35 52 31 47
-42 34 42 42 30 2D 43 51 4B 4F 44 20 20 20 20 20
-20 20 20 20 20 20 20 00 80 CE 95 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/mainboard/system76/mtl/variants/darp10/board.fmd

@@ -1,13 +0,0 @@
-FLASH 32M {
-	SI_DESC 16K
-	SI_GBE 8K
-	SI_ME 10640K
-	SI_BIOS@16M 16M {
-		RW_MRC_CACHE 64K
-		SMMSTORE(PRESERVE) 256K
-		WP_RO {
-			FMAP 4K
-			COREBOOT(CBFS)
-		}
-	}
-}

src/mainboard/system76/mtl/variants/darp10/board_info.txt

@@ -1,2 +0,0 @@
-Board name: darp10
-Release year: 2024

src/mainboard/system76/mtl/variants/darp10/gpio.c

@@ -1,216 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mainboard/gpio.h>
-#include <soc/gpio.h>
-
-static const struct pad_config gpio_table[] = {
-	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
-	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
-	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
-	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
-	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
-	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
-	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET_N
-	// GPP_A07 missing
-	// GPP_A08 missing
-	// GPP_A09 missing
-	// GPP_A10 missing
-	PAD_CFG_GPO(GPP_A11, 0, DEEP), // ADDS_CODE
-	PAD_CFG_GPI(GPP_A12, NONE, DEEP), // WLAN_WAKEUP#
-	PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), // M2_SSD2_RST#
-	PAD_NC(GPP_A14, NONE),
-	PAD_NC(GPP_A15, NONE), // CPU_SWI# (test point)
-	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALRT0#
-	PAD_NC(GPP_A17, NONE), // TP_ATTN#_A17
-	PAD_NC(GPP_A18, NONE),
-	PAD_NC(GPP_A19, NONE),
-	PAD_NC(GPP_A20, NONE),
-	PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), // PMC_I2C_INT
-
-	PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), // TP_ATTN#_B00
-	PAD_NC(GPP_B01, NONE),
-	PAD_NC(GPP_B02, NONE),
-	PAD_NC(GPP_B03, NONE),
-	PAD_CFG_GPO(GPP_B04, 0, DEEP), // NO REBOOT strap
-	PAD_CFG_GPO(GPP_B05, 0, DEEP), // CPU_KBCRST# (test point)
-	PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN
-	PAD_NC(GPP_B07, NONE),
-	PAD_NC(GPP_B08, NONE),
-	PAD_NC(GPP_B09, NONE),
-	PAD_NC(GPP_B10, NONE),
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // HDMI_HPD
-	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST#
-	PAD_CFG_GPI(GPP_B14, NONE, DEEP), // Top swap override strap
-	PAD_CFG_GPI(GPP_B15, NONE, DEEP), // GPP_B15_USB2_OC0_N
-	PAD_NC(GPP_B16, NONE),
-	PAD_NC(GPP_B17, NONE),
-	PAD_CFG_GPO(GPP_B18, 1, DEEP), // PCH_BT_EN
-	PAD_CFG_GPO(GPP_B19, 1, DEEP), // WIFI_RF_EN
-	PAD_NC(GPP_B20, NONE),
-	PAD_CFG_GPO(GPP_B21, 0, PLTRST), // TCP_RETIMER_FORCE_PWR
-	PAD_NC(GPP_B22, NONE),
-	PAD_NC(GPP_B23, NONE),
-
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
-	PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // TLS confidentiality strap
-	PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK
-	PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA
-	PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // eSPI disabled strap
-	PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // PMC_I2C_SCL
-	PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // PMC_I2C_SDA
-	PAD_NC(GPP_C08, NONE),
-	PAD_NC(GPP_C09, NONE),
-	PAD_NC(GPP_C10, NONE),
-	PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // CPU_LAN_CLKREQ#
-	PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // CPU_CARD_CLKREQ#
-	PAD_NC(GPP_C13, NONE),
-	// GPP_C14 missing
-	PAD_CFG_GPO(GPP_C15, 0, DEEP), // GPP_C15_STRAP
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD
-	PAD_NC(GPP_C18, NONE),
-	PAD_NC(GPP_C19, NONE),
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA
-	PAD_NC(GPP_C22, NONE),
-	PAD_NC(GPP_C23, NONE),
-
-	PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON
-	PAD_CFG_GPO(GPP_D01, 1, DEEP), // SSD2_PWR_EN
-	PAD_CFG_GPO(GPP_D02, 1, DEEP), // M2_SSD1_RST#
-	PAD_NC(GPP_D03, NONE),
-	PAD_NC(GPP_D04, NONE),
-	PAD_CFG_GPO(GPP_D05, 1, DEEP), // SSD1_PWR_EN
-	PAD_NC(GPP_D06, NONE),
-	PAD_NC(GPP_D07, NONE),
-	PAD_NC(GPP_D08, NONE),
-	PAD_NC(GPP_D09, NONE),
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK
-	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC
-	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
-	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDI0
-	PAD_NC(GPP_D14, NONE),
-	PAD_NC(GPP_D15, NONE),
-	PAD_CFG_GPO(GPP_D16, 0, DEEP), // GPIO_SPK_MUTE
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_RST#
-	PAD_NC(GPP_D18, NONE),
-	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // CPU_SSD1_CLKREQ#
-	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // CPU_SSD2_CLKREQ#
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), // CPU_WLAN_CLKREQ#
-	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
-
-	PAD_NC(GPP_E00, NONE),
-	_PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x3000), // TPM_PIRQ#
-	PAD_CFG_GPI(GPP_E02, NONE, DEEP), // BOARD_ID4
-	PAD_CFG_GPI(GPP_E03, NONE, DEEP), // CNVI_WAKE#
-	PAD_NC(GPP_E04, NONE),
-	PAD_NC(GPP_E05, NONE),
-	PAD_CFG_GPO(GPP_E06, 0, DEEP), // JTAG ODT disable strap
-	PAD_NC(GPP_E07, NONE),
-	PAD_NC(GPP_E08, NONE),
-	PAD_CFG_GPI(GPP_E09, NONE, DEEP), // GPP_E9_USB2_OC0_N
-	PAD_NC(GPP_E10, NONE),
-	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID6
-	PAD_NC(GPP_E12, NONE),
-	PAD_NC(GPP_E13, NONE),
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
-	PAD_NC(GPP_E15, NONE),
-	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), // VRALERT#
-	PAD_CFG_GPO(GPP_E17, 0, DEEP), // BOARD_ID5
-	// GPP_E18 missing
-	// GPP_E19 missing
-	// GPP_E20 missing
-	// GPP_E21 missing
-	PAD_CFG_GPO(GPP_E22, 0, DEEP), // DNX_FORCE_RELOAD
-
-	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT
-	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
-	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT
-	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
-	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST#
-	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ
-	PAD_CFG_GPO(GPP_F06, 0, DEEP), // CNVI_GNSS_PA_BLANKING
-	PAD_NC(GPP_F07, NONE),
-	PAD_NC(GPP_F08, NONE),
-	PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET
-	PAD_NC(GPP_F10, NONE),
-	PAD_CFG_GPO(GPP_F11, 0, DEEP), // BOARD_ID3
-	PAD_NC(GPP_F12, NONE), // I2C_SCL_CODEC
-	PAD_NC(GPP_F13, NONE), // I2C_SDA_CODEC
-	PAD_CFG_GPO(GPP_F14, 0, DEEP), // BOARD_ID1
-	PAD_CFG_GPO(GPP_F15, 0, DEEP), // BOARD_ID2
-	PAD_NC(GPP_F16, NONE),
-	PAD_NC(GPP_F17, NONE),
-	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CPU_CCD_WP#
-	PAD_NC(GPP_F19, NONE),
-	PAD_CFG_GPO(GPP_F20, 0, DEEP), // SVID support strap
-	PAD_NC(GPP_F21, NONE),
-	PAD_NC(GPP_F22, NONE),
-	PAD_NC(GPP_F23, NONE),
-
-	PAD_CFG_GPO(GPP_H00, 0, DEEP), // eSPI flash sharing mode strap
-	PAD_CFG_GPO(GPP_H01, 0, DEEP), // SPI flash descriptor recovery strap
-	PAD_NC(GPP_H02, NONE),
-	// GPP_H03 missing
-	PAD_CFG_GPO(GPP_H04, 0, DEEP), // CNVI_MFUART2_RXD
-	PAD_CFG_GPO(GPP_H05, 0, DEEP), // CNVI_MFUART2_TXD
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // I2C3_SDA (Pantone)
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // I2C3_SCL (Pantone)
-	// GPP_H08 (UART0_RXD) configured in bootblock
-	// GPP_H09 (UART0_TXD) configured in bootblock
-	PAD_CFG_GPO(GPP_H10, 0, DEEP),
-	PAD_CFG_GPO(GPP_H11, 0, DEEP),
-	PAD_CFG_GPO(GPP_H12, 0, DEEP),
-	PAD_NC(GPP_H13, NONE),
-	PAD_NC(GPP_H14, NONE),
-	PAD_NC(GPP_H15, NONE),
-	PAD_NC(GPP_H16, NONE),
-	PAD_NC(GPP_H17, NONE),
-	// GPP_H18 missing
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C_SDA_TP
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C_SCL_TP
-	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA
-	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL
-
-	PAD_NC(GPP_S00, NONE),
-	PAD_NC(GPP_S01, NONE),
-	PAD_NC(GPP_S02, NONE), // DMIC_CLK_A1
-	PAD_NC(GPP_S03, NONE), // DMIC_DATA_A1
-	PAD_NC(GPP_S04, NONE),
-	PAD_NC(GPP_S05, NONE),
-	PAD_NC(GPP_S06, NONE),
-	PAD_NC(GPP_S07, NONE),
-
-	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW#
-	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT
-	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // LAN_WAKEUP#
-	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PWR_BTN#
-	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH
-	PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1), // SUSC#_PCH
-	PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1), // SLP_A#
-	// GPP_V07 missing
-	PAD_CFG_NF(GPP_V08, UP_20K, DEEP, NF1), // SUS_CLK
-	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // SLP_WLAN#
-	PAD_NC(GPP_V10, NONE),
-	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), // LANPHYPC
-	PAD_CFG_GPO(GPP_V12, 0, DEEP), // SLP_LAN#
-	// GPP_V13 missing
-	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // PCIE_WAKE#
-	// GPP_V15 missing
-	// GPP_V16 missing
-	// GPP_V17 missing
-	// GPP_V18 missing
-	// GPP_V19 missing
-	// GPP_V20 missing
-	// GPP_V21 missing
-	PAD_NC(GPP_V22, NONE),
-	PAD_NC(GPP_V23, NONE),
-};
-
-void mainboard_configure_gpios(void)
-{
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}

src/mainboard/system76/mtl/variants/darp10/gpio_early.c

@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mainboard/gpio.h>
-#include <soc/gpio.h>
-
-static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
-	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
-	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
-};
-
-void mainboard_configure_early_gpios(void)
-{
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}

src/mainboard/system76/mtl/variants/darp10/hda_verb.c

@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	/* Realtek, ALC245 */
-	0x10ec0245, /* Vendor ID */
-	0x1558a763, /* Subsystem ID */
-	40, /* Number of entries */
-	//AZALIA_SUBVENDOR(0, 0x1558a763),
-	AZALIA_SUBVENDOR(0, 0x1558a743),
-	AZALIA_RESET(1),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
-	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d),
-	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
-
-	0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
-	0x0205004a, 0x02042010, 0x02050038, 0x02047909,
-	0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
-	0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
-	0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
-	0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
-	0x05450000, 0x05442000, 0x0545001d, 0x05440800,
-	0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
-	0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
-	0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
-	0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
-	0x02050010, 0x02040020, 0x02050010, 0x02040020,
-	0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
-	0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
-	0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
-	0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
-	0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
-	0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
-	0x02050003, 0x02040002, 0x02050069, 0x02040000,
-	0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
-	0x02236100, 0x02235100, 0x00920011, 0x00970610,
-	0x00936000, 0x00935000, 0x0205000d, 0x0204a020,
-	0x00220011, 0x00270610, 0x0023a046, 0x00239046,
-	0x0173b000, 0x01770740, 0x05a50001, 0x05a4001f,
-	0x05c5000f, 0x05c40003, 0x02050036, 0x020437d7,
-	0x0143b000, 0x01470740, 0x02050010, 0x02040020,
-	0x01470c02, 0x01470c02,
-
-	// XXX: Duplicate last 2 u32s to keep in 4-dword blocks
-	0x01470c02, 0x01470c02,
-};
-
-const u32 pc_beep_verbs[] = {};
-
-AZALIA_ARRAY_SIZES;

src/mainboard/system76/mtl/variants/darp10/overridetree.cb

@@ -1,91 +0,0 @@
-chip soc/intel/meteorlake
-	device domain 0 on
-		subsystemid 0x1558 0xa743 inherit
-
-		device ref tbt_pcie_rp0 on end
-		device ref tcss_xhci on end
-		device ref tcss_dma0 on end
-		device ref xhci on
-			register "usb2_ports" = "{
-				[0] = USB2_PORT_MID(OC_SKIP),	/* J_AUD1 / AJ_USB3_1 */
-				[1] = USB2_PORT_MID(OC_SKIP),	/* J_TYPEC1 */
-				[2] = USB2_PORT_MID(OC_SKIP),	/* J_USB3_1 */
-				[5] = USB2_PORT_MID(OC_SKIP),	/* TBT */
-				[6] = USB2_PORT_MID(OC_SKIP),	/* Camera */
-				[9] = USB2_PORT_MID(OC_SKIP),	/* Bluetooth */
-			}"
-			register "usb3_ports" = "{
-				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_AUD1 / AJ_USB3_1 */
-				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_USB3_1 */
-			}"
-		end
-		device ref i2c0 on
-			# Touchpad I2C bus
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN0412""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""FTCS1000""
-				register "generic.desc" = ""FocalTech Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 38 on end
-			end
-		end
-		device ref pcie_rp5 on
-			# GLAN
-			register "pcie_rp[PCH_RP(5)]" = "{
-				.clk_src = 2,
-				.clk_req = 2,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
-			}"
-			register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING"
-			device pci 00.0 on end
-		end
-		device ref pcie_rp6 on
-			# Card Reader
-			register "pcie_rp[PCH_RP(6)]" = "{
-				.clk_src = 3,
-				.clk_req = 3,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp8 on
-			# WLAN
-			register "pcie_rp[PCH_RP(8)]" = "{
-				.clk_src = 5,
-				.clk_req = 5,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp10 on
-			# SSD2
-			# XXX: Schematics show RP[13:16] used
-			register "pcie_rp[PCH_RP(10)]" = "{
-				.clk_src = 8,
-				.clk_req = 8,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp11 on
-			# SSD1
-			# XXX: Schematics show RP[17:20] used
-			register "pcie_rp[PCH_RP(11)]" = "{
-				.clk_src = 7,
-				.clk_req = 7,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref hda on
-			subsystemid 0x1558 0xa763
-		end
-		device ref gbe on end
-	end
-end

src/mainboard/system76/mtl/variants/darp10/ramstage.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/ramstage.h>
-
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	// XXX: Enabling C10 reporting causes system to constantly enter and
-	// exit opportunistic suspend when idle.
-	params->PchEspiHostC10ReportEnable = 0;
-}

src/mainboard/system76/mtl/variants/darp10/romstage.c

@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/meminit.h>
-#include <soc/romstage.h>
-
-void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
-	const struct mb_cfg board_cfg = {
-		.type = MEM_TYPE_DDR5,
-		.ect = true,
-	};
-	const struct mem_spd spd_info = {
-		.topo = MEM_TOPO_DIMM_MODULE,
-		.smbus = {
-			[0] = { .addr_dimm[0] = 0x50, },
-			[1] = { .addr_dimm[0] = 0x52, },
-		},
-	};
-	const bool half_populated = false;
-
-	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
-	mupd->FspmConfig.GpioOverride = 0;
-
-	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
-}

src/mainboard/system76/mtl/variants/lemp13/board.fmd

@@ -1,12 +0,0 @@
-FLASH 32M {
-	SI_DESC 16K
-	SI_ME 10128K
-	SI_BIOS@16M 16M {
-		RW_MRC_CACHE 64K
-		SMMSTORE(PRESERVE) 256K
-		WP_RO {
-			FMAP 4K
-			COREBOOT(CBFS)
-		}
-	}
-}

src/mainboard/system76/mtl/variants/lemp13/board_info.txt

@@ -1,2 +0,0 @@
-Board name: lemp13
-Release year: 2024

src/mainboard/system76/mtl/variants/lemp13/gpio.c

@@ -1,208 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mainboard/gpio.h>
-#include <soc/gpio.h>
-
-static const struct pad_config gpio_table[] = {
-	PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC
-	PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC
-	PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC
-	PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC
-	PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC#
-	PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC
-	PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET#
-	PAD_NC(GPP_A07, NONE),
-	PAD_NC(GPP_A08, NONE),
-	PAD_NC(GPP_A09, NONE),
-	PAD_NC(GPP_A10, NONE),
-	PAD_CFG_GPO(GPP_A11, 0, PLTRST),
-	PAD_NC(GPP_A12, NONE),
-	PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST),
-	PAD_CFG_TERM_GPO(GPP_A14, 0, UP_20K, PLTRST),
-	PAD_CFG_TERM_GPO(GPP_A15, 0, UP_20K, PLTRST),
-	PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1),
-	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
-	PAD_CFG_TERM_GPO(GPP_A18, 0, UP_20K, PLTRST),
-	PAD_CFG_TERM_GPO(GPP_A19, 0, UP_20K, DEEP),
-	PAD_CFG_TERM_GPO(GPP_A20, 0, NATIVE, DEEP),
-	PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1),
-	_PAD_CFG_STRUCT(GPP_B00, 0x40100100, 0x0000),
-	PAD_CFG_GPO(GPP_B01, 0, PLTRST),
-	PAD_CFG_GPO(GPP_B02, 0, PLTRST),
-	PAD_CFG_GPO(GPP_B03, 0, PLTRST),
-	PAD_CFG_GPO(GPP_B04, 0, PLTRST),
-	PAD_CFG_GPO(GPP_B05, 1, PLTRST),
-	PAD_CFG_GPO(GPP_B06, 0, DEEP),
-	PAD_CFG_GPO(GPP_B07, 1, DEEP),
-	PAD_CFG_GPO(GPP_B08, 1, DEEP),
-	PAD_CFG_GPI(GPP_B09, NONE, DEEP),
-	PAD_CFG_GPI(GPP_B10, NONE, DEEP),
-	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // CPU_HDMI_HPD
-	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1),
-	PAD_CFG_GPO(GPP_B14, 0, PLTRST),
-	PAD_CFG_GPI(GPP_B15, NONE, DEEP),
-	PAD_CFG_GPI(GPP_B16, NONE, DEEP),
-	PAD_CFG_GPO(GPP_B17, 1, PLTRST), // HDMI_EN
-	PAD_CFG_GPO(GPP_B18, 1, PLTRST),
-	PAD_CFG_GPO(GPP_B19, 1, PLTRST),
-	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
-	PAD_CFG_GPO(GPP_B21, 0, PLTRST),
-	PAD_CFG_GPI(GPP_B22, NONE, DEEP),
-	PAD_CFG_GPO(GPP_B23, 1, DEEP),
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK_DDR
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA_DDR
-	PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // GPP_C2_STRAP
-	PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK
-	PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA
-	PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // GPP_C5_STRAP
-	PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // TBT_I2C_SCL
-	PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // TBT_I2C_SDA
-	PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1), // GPP_C08_TEST
-	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), // CARD_CLKREQ
-	PAD_CFG_GPO(GPP_C10, 0, PLTRST), // 5G_PCIE_CLKREQ
-	PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // WLAN_CLKREQ
-	PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // GPP_C13-TEST (typo from schematic)
-	PAD_CFG_GPO(GPP_C13, 1, DEEP),
-	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), // GPP_C15
-	// GPP_C16 (TBTA_LSX0_TXD) configured by FSP
-	// GPP_C17 (TBTA_LSX0_RXD) configured by FSP
-	// GPP_C18 not connected
-	// GPP_C19 not connected
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA
-	// GPP_C22 not connected
-	// GPP_C23 not connected
-	PAD_CFG_GPO(GPP_D00, 1, PLTRST),
-	PAD_CFG_GPO(GPP_D01, 1, PLTRST),
-	PAD_CFG_GPO(GPP_D02, 1, PLTRST),
-	PAD_NC(GPP_D03, NONE),
-	PAD_CFG_GPO(GPP_D04, 0, PLTRST),
-	PAD_CFG_GPO(GPP_D05, 1, PLTRST),
-	PAD_CFG_GPO(GPP_D06, 0, PLTRST),
-	PAD_CFG_GPO(GPP_D07, 0, PLTRST),
-	PAD_CFG_GPO(GPP_D08, 0, PLTRST),
-	PAD_CFG_GPO(GPP_D09, 0, PLTRST),
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_D14, 0, PLTRST),
-	PAD_CFG_GPO(GPP_D15, 0, PLTRST),
-	PAD_CFG_GPO(GPP_D16, 0, DEEP),
-	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-	PAD_NC(GPP_D18, NONE), // GPP_D18-TEST
-	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // SSD2_CLKREQ
-	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // SSD1_CLKREQ
-	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_E00, 0, PLTRST),
-	_PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x1000),
-	PAD_CFG_GPI(GPP_E02, NONE, DEEP),
-	PAD_NC(GPP_E03, NONE),
-	PAD_CFG_GPO(GPP_E04, 0, PLTRST),
-	PAD_CFG_GPO(GPP_E05, 0, PLTRST),
-	PAD_CFG_GPI(GPP_E06, NONE, DEEP),
-	PAD_CFG_GPO(GPP_E07, 0, PLTRST),
-	PAD_CFG_GPO(GPP_E08, 0, PLTRST),
-	PAD_CFG_GPI(GPP_E09, NONE, DEEP),
-	PAD_CFG_GPO(GPP_E10, 0, PLTRST),
-	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
-	_PAD_CFG_STRUCT(GPP_E12, 0x84002200, 0x0000),
-	_PAD_CFG_STRUCT(GPP_E13, 0x44002100, 0x0000),
-	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_E15, 0, PLTRST),
-	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),
-	PAD_CFG_GPO(GPP_E17, 0, PLTRST),
-	PAD_NC(GPP_E18, NONE),
-	PAD_NC(GPP_E19, NONE),
-	PAD_NC(GPP_E20, NONE),
-	PAD_NC(GPP_E21, NONE),
-	PAD_CFG_TERM_GPO(GPP_E22, 0, DN_20K, PLTRST),
-	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_F07, DN_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_F08, DN_20K, DEEP, NF1),
-	PAD_CFG_GPI(GPP_F09, NONE, DEEP),
-	PAD_NC(GPP_F10, NONE),
-	PAD_CFG_GPO(GPP_F11, 0, PLTRST),
-	_PAD_CFG_STRUCT(GPP_F12, 0x44002300, 0x0000), // AMP_SMB_CLK
-	_PAD_CFG_STRUCT(GPP_F13, 0x44002300, 0x0000), // AMP_SMB_DATA
-	PAD_CFG_GPO(GPP_F14, 0, PLTRST),
-	PAD_CFG_GPO(GPP_F15, 0, PLTRST),
-	PAD_CFG_GPO(GPP_F16, 0, PLTRST),
-	PAD_CFG_GPO(GPP_F17, 0, PLTRST),
-	PAD_CFG_GPO(GPP_F18, 0, DEEP),
-	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
-	PAD_CFG_GPO(GPP_F20, 0, PLTRST),
-	PAD_CFG_GPO(GPP_F21, 0, PLTRST),
-	PAD_CFG_GPO(GPP_F22, 0, PLTRST),
-	PAD_CFG_GPO(GPP_F23, 0, PLTRST),
-	PAD_CFG_GPO(GPP_H00, 0, PLTRST),
-	PAD_CFG_GPO(GPP_H01, 0, PLTRST),
-	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
-	PAD_NC(GPP_H03, NONE),
-	PAD_NC(GPP_H04, NONE),
-	PAD_NC(GPP_H05, NONE),
-	PAD_NC(GPP_H06, NONE),
-	PAD_NC(GPP_H07, NONE),
-	PAD_NC(GPP_H08, NONE),
-	PAD_NC(GPP_H09, NONE),
-	PAD_CFG_GPO(GPP_H10, 0, PLTRST),
-	PAD_CFG_GPO(GPP_H11, 0, PLTRST),
-	PAD_NC(GPP_H12, NONE),
-	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
-	PAD_CFG_GPO(GPP_H15, 0, PLTRST),
-	PAD_CFG_GPO(GPP_H16, 0, PLTRST),
-	PAD_CFG_GPO(GPP_H17, 0, PLTRST),
-	PAD_NC(GPP_H18, NONE),
-	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-	PAD_CFG_GPO(GPP_S00, 0, PLTRST),
-	PAD_CFG_GPO(GPP_S01, 0, PLTRST),
-	PAD_CFG_GPO(GPP_S02, 0, PLTRST),
-	PAD_CFG_GPO(GPP_S03, 0, PLTRST),
-	PAD_CFG_GPO(GPP_S04, 0, PLTRST),
-	PAD_CFG_GPO(GPP_S05, 0, PLTRST),
-	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
-	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1),
-	PAD_CFG_GPI(GPP_V07, NATIVE, DEEP),
-	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
-	PAD_NC(GPP_V12, NONE),
-	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
-	PAD_CFG_NF(GPP_V15, NONE, PLTRST, NF1),
-	PAD_CFG_GPO(GPP_V16, 0, PLTRST),
-	PAD_CFG_GPO(GPP_V17, 0, PLTRST),
-	PAD_NC(GPP_V18, NONE),
-	PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1),
-	PAD_NC(GPP_V20, NONE),
-	PAD_NC(GPP_V21, NONE),
-	PAD_NC(GPP_V22, NONE),
-	PAD_NC(GPP_V23, NONE),
-};
-
-void mainboard_configure_gpios(void)
-{
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}

src/mainboard/system76/mtl/variants/lemp13/gpio_early.c

@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mainboard/gpio.h>
-#include <soc/gpio.h>
-
-static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK
-	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA
-	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX
-	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX
-};
-
-void mainboard_configure_early_gpios(void)
-{
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}

src/mainboard/system76/mtl/variants/lemp13/hda_verb.c

@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	/* Realtek, ALC245 */
-	0x10ec0245, /* Vendor ID */
-	0x15582624, /* Subsystem ID */
-	34, /* Number of entries */
-
-	AZALIA_SUBVENDOR(0, 0x15582624),
-	AZALIA_RESET(1),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
-	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x14, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d),
-	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
-
-	0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
-	0x0205004a, 0x02042010, 0x02050038, 0x02046909,
-	0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
-	0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
-	0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
-	0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
-	0x05450000, 0x05442000, 0x0545001d, 0x05440800,
-	0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
-	0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
-	0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
-	0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
-	0x02050010, 0x02040020, 0x02050010, 0x02040020,
-	0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
-	0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
-	0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
-	0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
-	0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
-	0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
-	0x02050003, 0x02040002, 0x02050069, 0x02040000,
-	0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
-	0x02050010, 0x02040020, 0x02050010, 0x02040020,
-};
-
-const u32 pc_beep_verbs[] = {};
-
-AZALIA_ARRAY_SIZES;

src/mainboard/system76/mtl/variants/lemp13/overridetree.cb

@@ -1,120 +0,0 @@
-chip soc/intel/meteorlake
-	#TODO: POWER LIMITS
-	#register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
-	#	.tdp_pl1_override = 15,
-	#	.tdp_pl2_override = 46,
-	#}"
-
-	device domain 0 on
-		subsystemid 0x1558 0x2624 inherit
-
-		device ref tbt_pcie_rp0 on end
-		device ref tcss_xhci on
-			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
-			#TODO: TCP1 is used as USB Type-A
-			register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
-			#TODO: TCP2 is used as HDMI
-			#TODO: TCP3 goes to redriver, then mux, then USB Type-C
-			register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
-			chip drivers/usb/acpi
-				device ref tcss_root_hub on
-					chip drivers/usb/acpi
-						register "desc" = ""TBT Type-C""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device ref tcss_usb3_port0 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB Type-A""
-						register "type" = "UPC_TYPE_USB3_A"
-						device ref tcss_usb3_port1 on end
-					end
-					chip drivers/usb/acpi
-						register "desc" = ""USB Type-C""
-						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
-						device ref tcss_usb3_port3 on end
-					end
-				end
-			end
-		end
-		device ref tcss_dma0 on end
-		device ref xhci on
-			register "usb2_ports" = "{
-				[0] = USB2_PORT_MID(OC_SKIP),		/* TODO: USB TYPEA port1 GEN2 */
-				[1] = USB2_PORT_MID(OC_SKIP),		/* TODO: USB TYPEA port2 GEN1 */
-				[2] = USB2_PORT_TYPE_C(OC_SKIP),	/* TODO: TBT TYPEC USB2.0 */
-				[4] = USB2_PORT_TYPE_C(OC_SKIP),	/* TODO: TYPEC USB2.0 */
-				[6] = USB2_PORT_MID(OC_SKIP),		/* Camera */
-				[9] = USB2_PORT_MID(OC_SKIP),		/* Bluetooth */
-			}"
-			register "usb3_ports" = "{
-				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* TODO: USB port1 GEN1 */
-			}"
-		end
-
-		device ref i2c0 on
-			# Touchpad I2C bus
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN0412""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""FTCS1000""
-				register "generic.desc" = ""FocalTech Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 38 on end
-			end
-		end
-		device ref i2c5 on
-			# Smart Amplifier I2C bus
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
-			chip drivers/i2c/tas5825m
-				register "id" = "0"
-				device i2c 4e on end # (8bit address: 0x9c)
-			end
-		end
-
-		device ref pcie_rp1 on
-			# PCH RP#1 x1, Clock 0 (CARD)
-			register "pcie_rp[PCH_RP(1)]" = "{
-				.clk_src = 0,
-				.clk_req = 0,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp2 on
-			# PCH RP#2 x1, Clock 2 (WLAN)
-			register "pcie_rp[PCH_RP(2)]" = "{
-				.clk_src = 2,
-				.clk_req = 2,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp10 on
-			# PCH RP#10 x4, Clock 7 (SSD2)
-			# This uses signals PCIE_13 through PCIE_16 in the schematics
-			# but is identified as root port 10 in firmware.
-			register "pcie_rp[PCH_RP(10)]" = "{
-				.clk_src = 7,
-				.clk_req = 7,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp11 on
-			# CPU RP#11 x4, Clock 8 (SSD1)
-			# This uses signals PCIE_17 through PCIE_20 in the schematics
-			# but is identified as root port 11 in firmware.
-			register "pcie_rp[PCIE_RP(11)]" = "{
-				.clk_src = 8,
-				.clk_req = 8,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-	end
-end

src/mainboard/system76/mtl/variants/lemp13/ramstage.c

@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/ramstage.h>
-
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	// TODO: Pin Mux settings
-
-	// Enable TCP1 and TCP3 USB-A conversion
-	// BIT 0:3 is mapping to PCH XHCI USB2 port
-	// BIT 4:5 is reserved
-	// BIT 6 is orientational
-	// BIT 7 is enable
-	params->EnableTcssCovTypeA[1] = 0x81;
-	params->EnableTcssCovTypeA[3] = 0x85;
-
-	// Disable reporting CPU C10 state over eSPI (causes LED flicker).
-	params->PchEspiHostC10ReportEnable = 0;
-}

src/mainboard/system76/mtl/variants/lemp13/romstage.c

@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/meminit.h>
-#include <soc/romstage.h>
-
-void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
-	const struct mb_cfg board_cfg = {
-		.type = MEM_TYPE_DDR5,
-		.ect = true,
-		.LpDdrDqDqsReTraining = 1,
-	};
-	const struct mem_spd spd_info = {
-		.topo = MEM_TOPO_MIXED,
-		.cbfs_index = 0,
-		.smbus[1] = { .addr_dimm[0] = 0x52, },
-	};
-	const bool half_populated = false;
-
-	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
-	mupd->FspmConfig.GpioOverride = 0;
-
-	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
-}

src/mainboard/system76/oryp5/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/oryp5/acpi/mainboard.asl

@@ -10,7 +10,6 @@ Scope (\_SB)
 {
 	#include "sleep.asl"
 	Scope (PCI0) {
-		#include "backlight.asl"
 		Device (PEGP) {
 			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
 			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>

src/mainboard/system76/oryp5/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/oryp5/dsdt.asl

@@ -19,6 +19,7 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/oryp6/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/oryp6/acpi/mainboard.asl

@@ -9,7 +9,6 @@
 Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
-		#include "backlight.asl"
 		Device (PEGP) {
 			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
 			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>

src/mainboard/system76/oryp6/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/oryp6/dsdt.asl

@@ -18,6 +18,7 @@ DefinitionBlock(
 	Device (\_SB.PCI0) {
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/rpl/Kconfig

@@ -9,8 +9,6 @@ config BOARD_SYSTEM76_RPL_COMMON
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_LOCKDOWN
-	select ENABLE_TCSS_DISPLAY_DETECTION
-	select ENABLE_TCSS_USB_DETECTION
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
@@ -86,16 +84,6 @@ config BOARD_SYSTEM76_ORYP11
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
-config BOARD_SYSTEM76_ORYP12
-	select BOARD_SYSTEM76_RPL_COMMON
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
-	select DRIVERS_I2C_TAS5825M
-	select DRIVERS_INTEL_DTBT
-	select EC_SYSTEM76_EC_DGPU
-	select PCIEXP_HOTPLUG
-	select SOC_INTEL_ALDERLAKE_PCH_S
-
 config BOARD_SYSTEM76_SERW13
 	select BOARD_SYSTEM76_RPL_COMMON
 	select DRIVERS_GFX_NVIDIA
@@ -119,7 +107,6 @@ config VARIANT_DIR
 	default "gaze18" if BOARD_SYSTEM76_GAZE18
 	default "lemp12" if BOARD_SYSTEM76_LEMP12
 	default "oryp11" if BOARD_SYSTEM76_ORYP11
-	default "oryp12" if BOARD_SYSTEM76_ORYP12
 	default "serw13" if BOARD_SYSTEM76_SERW13
 
 config OVERRIDE_DEVICETREE
@@ -134,7 +121,6 @@ config MAINBOARD_PART_NUMBER
 	default "gaze18" if BOARD_SYSTEM76_GAZE18
 	default "lemp12" if BOARD_SYSTEM76_LEMP12
 	default "oryp11" if BOARD_SYSTEM76_ORYP11
-	default "oryp12" if BOARD_SYSTEM76_ORYP12
 	default "serw13" if BOARD_SYSTEM76_SERW13
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
@@ -144,7 +130,7 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "Galago Pro" if BOARD_SYSTEM76_GALP7
 	default "Gazelle" if BOARD_SYSTEM76_GAZE18
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP12
-	default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
+	default "Oryx Pro" if BOARD_SYSTEM76_ORYP11
 	default "Serval WS" if BOARD_SYSTEM76_SERW13
 
 config MAINBOARD_VERSION
@@ -156,7 +142,6 @@ config MAINBOARD_VERSION
 	default "gaze18" if BOARD_SYSTEM76_GAZE18
 	default "lemp12" if BOARD_SYSTEM76_LEMP12
 	default "oryp11" if BOARD_SYSTEM76_ORYP11
-	default "oryp12" if BOARD_SYSTEM76_ORYP12
 	default "serw13" if BOARD_SYSTEM76_SERW13
 
 config CMOS_DEFAULT_FILE
@@ -176,12 +161,12 @@ config DRIVERS_GFX_NVIDIA_BRIDGE
 	default 0x02 if BOARD_SYSTEM76_BONW15
 
 config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
-	default 45 if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
+	default 45 if BOARD_SYSTEM76_ORYP11
 	default 55 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_SERW13
 	default 80 if BOARD_SYSTEM76_BONW15
 
 config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
-	default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
+	default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_SERW13
 
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"

src/mainboard/system76/rpl/Kconfig.name

@@ -24,8 +24,5 @@ config BOARD_SYSTEM76_LEMP12
 config BOARD_SYSTEM76_ORYP11
 	bool "oryp11"
 
-config BOARD_SYSTEM76_ORYP12
-	bool "oryp12"
-
 config BOARD_SYSTEM76_SERW13
 	bool "serw13"

src/mainboard/system76/rpl/Makefile.mk

@@ -14,6 +14,5 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
-ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
 
 SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD

src/mainboard/system76/rpl/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/rpl/acpi/mainboard.asl

@@ -11,8 +11,6 @@
 Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
-		#include "backlight.asl"
-
 #if CONFIG(DRIVERS_GFX_NVIDIA)
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(BOARD_SYSTEM76_BONW15)
 		Scope (PEG2) {

src/mainboard/system76/rpl/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/rpl/dsdt.asl

@@ -20,6 +20,7 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/alderlake/acpi/southbridge.asl>
 		#include <soc/intel/alderlake/acpi/tcss.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/rpl/variants/oryp12/board.fmd

@@ -1,12 +0,0 @@
-FLASH 32M {
-	SI_DESC 4K
-	SI_ME 3944K
-	SI_BIOS@16M 16M {
-		RW_MRC_CACHE 64K
-		SMMSTORE(PRESERVE) 256K
-		WP_RO {
-			FMAP 4K
-			COREBOOT(CBFS)
-		}
-	}
-}

src/mainboard/system76/rpl/variants/oryp12/board_info.txt

@@ -1,2 +0,0 @@
-Board name: oryp12
-Release year: 2024

src/mainboard/system76/rpl/variants/oryp12/gpio.c

@@ -1,296 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mainboard/gpio.h>
-#include <soc/gpio.h>
-
-static const struct pad_config gpio_table[] = {
-	/* ------- GPIO Group GPD ------- */
-	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW_N
-	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
-	PAD_NC(GPD2, NONE),
-	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
-	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
-	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
-	PAD_NC(GPD6, NONE), // SLP_A# (test)
-	PAD_NC(GPD7, NONE), // GPD_7 (strap)
-	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK
-	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
-	PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // SLP_S5# (test)
-	PAD_NC(GPD11, NONE),
-	PAD_NC(GPD12, NONE),
-
-	/* ------- GPIO Group GPP_A ------- */
-	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
-	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
-	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
-	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
-	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
-	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
-	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET#
-	PAD_NC(GPP_A7, NONE),
-	PAD_NC(GPP_A8, NONE),
-	PAD_NC(GPP_A9, NONE),
-	PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0
-	PAD_NC(GPP_A11, NONE),
-	PAD_NC(GPP_A12, NONE),
-	PAD_NC(GPP_A13, NONE),
-	PAD_NC(GPP_A14, NONE),
-
-	/* ------- GPIO Group GPP_B ------- */
-	_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // PIRQ#_TPM
-	PAD_CFG_GPI(GPP_B1, NONE, DEEP),
-	PAD_CFG_GPI(GPP_B2, NONE, DEEP), //CNVI_WAKE#
-	PAD_CFG_GPO(GPP_B3, 1, PLTRST), // BT_EN
-	PAD_NC(GPP_B4, NONE),
-	PAD_NC(GPP_B5, NONE),
-	PAD_NC(GPP_B6, NONE),
-	PAD_NC(GPP_B7, NONE), // M2_SSD2_RST#
-	PAD_NC(GPP_B8, NONE), // M2_SSD1_RST#
-	PAD_NC(GPP_B9, NONE), // M2_SSD1_PWR_EN
-	PAD_NC(GPP_B10, NONE), // M2_SSD2_PWR_EN
-	PAD_NC(GPP_B11, NONE),
-	PAD_NC(GPP_B12, NONE),
-	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
-	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
-	PAD_CFG_GPO(GPP_B15, 0, DEEP), // PS8461_SW (XXX: NC)
-	PAD_NC(GPP_B16, NONE),
-	PAD_NC(GPP_B17, NONE),
-	PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT#
-	PAD_CFG_GPO(GPP_B19, 1, DEEP), // PCH_WLAN_EN (XXX: NC)
-	PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3
-	_PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000), // GPP_B21_TBT_WAKE#
-	PAD_CFG_GPO(GPP_B22, 0, DEEP), // LAN_PLT_RST#
-	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal frequency bit 1 strap
-
-	/* ------- GPIO Group GPP_C ------- */
-	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
-	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
-	PAD_CFG_GPI(GPP_C2, NONE, DEEP), // PCH_PORT80_LED
-	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // GPPB_I2C2_SDA
-	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // GPPB_I2C2_SCL
-	PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C_5_SML0ALERT_N
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // I2C_SDA_AMP
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // I2C_SCL_AMP
-	PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
-	PAD_NC(GPP_C9, NONE),
-	PAD_NC(GPP_C10, NONE),
-	PAD_NC(GPP_C11, NONE),
-	PAD_NC(GPP_C12, NONE),
-	PAD_NC(GPP_C13, NONE),
-	PAD_NC(GPP_C14, NONE),
-	PAD_NC(GPP_C15, NONE),
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL
-	// GPP_C20 (UART2_RXD) configured in bootblock
-	// GPP_C21 (UART2_TXD) configured in bootblock
-	PAD_CFG_GPO(GPP_C22, 0, DEEP),
-	PAD_CFG_GPO(GPP_C23, 0, DEEP),
-
-	/* ------- GPIO Group GPP_D ------- */
-	PAD_NC(GPP_D0, NONE),
-	PAD_NC(GPP_D1, NONE),
-	PAD_NC(GPP_D2, NONE),
-	PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP
-	PAD_NC(GPP_D4, NONE), // GPP_D4_SML1CLK
-	PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N
-	// GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP
-	PAD_NC(GPP_D7, NONE), // M.2_BT_PCMIN
-	PAD_NC(GPP_D8, NONE), // M.2_BT_PCMCLK
-	PAD_NC(GPP_D9, NONE), // GPP_D9_SML0CLK
-	PAD_NC(GPP_D10, NONE), // GPP_D10_SML0DATA
-	PAD_NC(GPP_D11, NONE),
-	PAD_NC(GPP_D12, NONE),
-	PAD_NC(GPP_D13, NONE),
-	PAD_NC(GPP_D14, NONE),
-	PAD_NC(GPP_D15, NONE), // GPP_D15_SML1DATA
-	PAD_NC(GPP_D16, NONE),
-	PAD_NC(GPP_D17, NONE),
-	PAD_NC(GPP_D18, NONE),
-	PAD_NC(GPP_D19, NONE),
-	PAD_NC(GPP_D20, NONE),
-	PAD_NC(GPP_D21, NONE),
-	PAD_NC(GPP_D22, NONE),
-	PAD_NC(GPP_D23, NONE),
-
-	/* ------- GPIO Group GPP_E ------- */
-	PAD_NC(GPP_E0, NONE),
-	PAD_NC(GPP_E1, NONE),
-	PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI#
-	PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI#
-	PAD_NC(GPP_E4, NONE),
-	PAD_NC(GPP_E5, NONE),
-	PAD_NC(GPP_E6, NONE),
-	PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN#
-	PAD_NC(GPP_E8, NONE),
-	PAD_CFG_GPI(GPP_E9, NONE, DEEP), // GPP_E_9_USB_OC0_N
-	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // GPP_E_10_USB_OC1_N
-	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // GPP_E_11_USB_OC2_N
-	PAD_CFG_GPI(GPP_E12, NONE, DEEP), // GPP_E_12_USB_OC3_N
-	PAD_NC(GPP_E13, NONE),
-	PAD_NC(GPP_E14, NONE),
-	PAD_CFG_GPO(GPP_E15, 1, DEEP), // ROM_I2C_EN
-	PAD_NC(GPP_E16, NONE),
-	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST#
-	PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON
-	PAD_NC(GPP_E19, NONE),
-	PAD_NC(GPP_E20, NONE),
-	PAD_NC(GPP_E21, NONE),
-
-	/* ------- GPIO Group GPP_F ------- */
-	PAD_NC(GPP_F0, NONE),
-	PAD_NC(GPP_F1, NONE),
-	PAD_CFG_GPO(GPP_F2, 1, DEEP), // GPP_F2_TBT_RST#
-	PAD_NC(GPP_F3, NONE),
-	PAD_NC(GPP_F4, NONE),
-	PAD_CFG_GPI(GPP_F5, NONE, DEEP), // GPIO4_GC6_NVVDD_EN_R
-	PAD_NC(GPP_F6, NONE), // GPU_EVENT#
-	PAD_NC(GPP_F7, NONE),
-	PAD_CFG_GPI(GPP_F8, NONE, PLTRST), // GC6_FB_EN_PCH
-	// GPP_F9 (DGPU_PWR_EN) configured in bootblock
-	PAD_CFG_GPI(GPP_F10, NONE, DEEP), // GPP_F10
-	PAD_NC(GPP_F11, NONE), // CARD_RTD3_RST#
-	PAD_NC(GPP_F12, NONE),
-	PAD_NC(GPP_F13, NONE),
-	PAD_NC(GPP_F14, NONE),
-	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
-	PAD_NC(GPP_F16, NONE),
-	PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
-	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_FW_WP#
-	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
-	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
-	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
-	PAD_NC(GPP_F22, NONE),
-	PAD_NC(GPP_F23, NONE),
-
-	/* ------- GPIO Group GPP_G ------- */
-	PAD_NC(GPP_G0, NONE),
-	PAD_NC(GPP_G1, NONE),
-	PAD_NC(GPP_G2, NONE),
-	PAD_CFG_GPI(GPP_G3, NONE, DEEP), // L: W/Pantone, H: W/O Pantone
-	PAD_CFG_GPI(GPP_G4, NONE, DEEP), // L: BID_X2, H: BID_X6/X4
-	PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // GPP_G_5_SLP_DRAM_N
-	PAD_CFG_GPI(GPP_G6, NONE, DEEP),
-	PAD_CFG_GPI(GPP_G7, NONE, DEEP),
-
-	/* ------- GPIO Group GPP_H ------- */
-	PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP
-	PAD_NC(GPP_H1, NONE),
-	PAD_CFG_GPI(GPP_H2, NONE, DEEP), // LAN_GPIO_WAKE_N
-	// GPP_H3 (PEX_SSD2_CLKREQ#) configured by FSP
-	// GPP_H4 (PEX_SSD1_CLKREQ#) configured by FSP
-	// GPP_H5 (WLAN_CLKREQ#) configured by FSP
-	// GPP_H6 (CARD_CLKREQ#) configured by FSP
-	// GPP_H7 (LAN_CLKREQ#) configured by FSP
-	// GPP_H8 (PEG_CLKREQ#) configured by FSP
-	// GPP_H9 (TBT_CLKREQ#) configured by FSP
-	PAD_NC(GPP_H10, NONE),
-	PAD_NC(GPP_H11, NONE),
-	PAD_CFG_GPO(GPP_H12, 0, DEEP), // L: MAFS, H: SAFS
-	PAD_NC(GPP_H13, NONE),
-	PAD_NC(GPP_H14, NONE),
-	PAD_CFG_GPO(GPP_H15, 0, DEEP), // JTAG ODT: L: disabled, H: enabled
-	PAD_NC(GPP_H16, NONE),
-	PAD_NC(GPP_H17, NONE), // M2_WLAN_RST#
-	PAD_CFG_GPO(GPP_H18, 0, DEEP), // VCCSPI: L: 3.3V, H: 1.8V
-	PAD_NC(GPP_H19, NONE),
-	PAD_NC(GPP_H20, NONE),
-	PAD_CFG_GPO(GPP_H21, 0, DEEP), // TBT_MRESET_PCH
-	PAD_NC(GPP_H22, NONE),
-	PAD_NC(GPP_H23, NONE),
-
-	/* ------- GPIO Group GPP_I ------- */
-	PAD_NC(GPP_I0, NONE),
-	PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // CPU_DP_B_HPD
-	PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), // HDMI_HPD
-	PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), // CPU_DP_D_HPD
-	PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), // G_DP_A_HPD_L
-	PAD_CFG_GPO(GPP_I5, 0, DEEP), // GPIO_TBT_RESET
-	PAD_NC(GPP_I6, NONE),
-	PAD_NC(GPP_I7, NONE),
-	PAD_NC(GPP_I8, NONE),
-	PAD_NC(GPP_I9, NONE),
-	PAD_NC(GPP_I10, NONE),
-	PAD_CFG_GPI(GPP_I11, NONE, DEEP), // GPP_I_11_USB_OC4_N
-	PAD_CFG_GPI(GPP_I12, NONE, DEEP), // GPP_I_12_USB_OC5_N
-	PAD_CFG_GPI(GPP_I13, NONE, DEEP), // GPP_I_13_USB_OC6_N
-	PAD_CFG_GPI(GPP_I14, NONE, DEEP), // GPP_I_14_USB_OC7_N
-	PAD_NC(GPP_I15, NONE),
-	PAD_NC(GPP_I16, NONE),
-	PAD_NC(GPP_I17, NONE),
-	PAD_CFG_GPO(GPP_I18, 0, DEEP), // No Reboot: L: disable H: enable
-	PAD_NC(GPP_I19, NONE),
-	PAD_NC(GPP_I20, NONE),
-	PAD_NC(GPP_I21, NONE),
-	PAD_CFG_GPO(GPP_I22, 0, DEEP), // BIOS fetch routing:
-				       // L: SPI (MAF) or eSPI Flash Ch (SAF)
-				       // H: eSPI Peripheral Ch
-
-	/* ------- GPIO Group GPP_J ------- */
-	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
-	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE_N
-	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT
-	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
-	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT
-	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
-	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
-	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
-	PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU
-	PAD_NC(GPP_J9, NONE),
-	PAD_NC(GPP_J10, NONE),
-	PAD_NC(GPP_J11, NONE),
-
-	/* ------- GPIO Group GPP_K ------- */
-	_PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000), // TBCIO_PLUG_EVENT#
-	PAD_NC(GPP_K1, NONE),
-	PAD_NC(GPP_K2, NONE),
-	PAD_CFG_GPO(GPP_K3, 1, PLTRST), // TBT_RTD3_PWR_EN_R
-	PAD_CFG_TERM_GPO(GPP_K4, 0, UP_20K, DEEP), // TBT_FORCE_PWR_R
-	PAD_NC(GPP_K5, NONE),
-	// GPP_K6 not in schematics
-	// GPP_K7 not in schematics
-	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0
-	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1
-	// GPP_K10 not in schematics
-	PAD_NC(GPP_K11, NONE),
-
-	/* ------- GPIO Group GPP_R ------- */
-	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
-	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
-	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
-	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
-	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
-	PAD_CFG_GPO(GPP_R5, 0, DEEP), // PCH_MUTE (XXX: SMART_AMP_EN)
-	PAD_NC(GPP_R6, NONE),
-	PAD_NC(GPP_R7, NONE),
-	PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R
-	PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // PCH_EDP_HPD
-	PAD_NC(GPP_R10, NONE),
-	PAD_NC(GPP_R11, NONE),
-	PAD_NC(GPP_R12, NONE),
-	PAD_NC(GPP_R13, NONE),
-	PAD_NC(GPP_R14, NONE),
-	PAD_NC(GPP_R15, NONE),
-	// GPP_R16 (DGPU_RST#_PCH) configured in bootblock
-	PAD_NC(GPP_R17, NONE),
-	PAD_NC(GPP_R18, NONE),
-	PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI#
-	PAD_NC(GPP_R20, NONE),
-	PAD_NC(GPP_R21, NONE),
-
-	/* ------- GPIO Group GPP_S ------- */
-	PAD_NC(GPP_S0, NONE),
-	PAD_NC(GPP_S1, NONE),
-	PAD_NC(GPP_S2, NONE),
-	PAD_NC(GPP_S3, NONE),
-	PAD_NC(GPP_S4, NONE),
-	PAD_NC(GPP_S5, NONE),
-	PAD_NC(GPP_S6, NONE),
-	PAD_NC(GPP_S7, NONE),
-};
-
-void mainboard_configure_gpios(void)
-{
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}

src/mainboard/system76/rpl/variants/oryp12/gpio_early.c

@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mainboard/gpio.h>
-#include <soc/gpio.h>
-
-static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
-	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
-	PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
-	PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH
-};
-
-void mainboard_configure_early_gpios(void)
-{
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}

src/mainboard/system76/rpl/variants/oryp12/hda_verb.c

@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	/* Realtek, ALC1220 */
-	0x10ec1220, /* Vendor ID */
-	0x155866a6, /* Subsystem ID */
-	24, /* Number of entries */
-
-	0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb,
-
-	AZALIA_SUBVENDOR(0, 0x155866a6),
-	AZALIA_RESET(1),
-	AZALIA_PIN_CFG(0, 0x12, 0x90a60120),
-	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
-	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
-	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x18, 0x04a11030),
-	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
-	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
-	AZALIA_PIN_CFG(0, 0x1d, 0x40a7952d),
-	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
-
-	0x05b50000, 0x05b43530, 0x05750002, 0x05741400,
-	0x02050058, 0x02048ed1, 0x02050063, 0x0204e430,
-	0x02050016, 0x02048020, 0x02050016, 0x02048020,
-	0x02050043, 0x02043005, 0x02050058, 0x02048ed1,
-	0x02050063, 0x0204e430, 0x05b50000, 0x05b43530,
-	0x05750002, 0x05741400, 0x05b5000a, 0x05b45520,
-	0x02050042, 0x020486cb, 0x0143b000, 0x01470740,
-	0x02050036, 0x02042a6a, 0x02050008, 0x0204800b,
-	0x02050007, 0x020403c3, 0x02050007, 0x020403c3,
-	0x0205001b, 0x02044002, 0x0205001b, 0x02044002,
-};
-
-const u32 pc_beep_verbs[] = {};
-
-AZALIA_ARRAY_SIZES;

src/mainboard/system76/rpl/variants/oryp12/include/variant/gpio.h

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_GPIO_H
-#define VARIANT_GPIO_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_R16
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_SSID	0x66a61558
-
-#endif

src/mainboard/system76/rpl/variants/oryp12/overridetree.cb

@@ -1,122 +0,0 @@
-chip soc/intel/alderlake
-	# Support 5600 MT/s memory
-	register "max_dram_speed_mts" = "5600"
-
-	device domain 0 on
-		subsystemid 0x1558 0x66a6 inherit
-
-		device ref xhci on
-			register "usb2_ports" = "{
-				[0] = USB2_PORT_MID(OC_SKIP),		// J_AUD1
-				[2] = USB2_PORT_MID(OC_SKIP),		// J_TYPEC2
-				[5] = USB2_PORT_MID(OC_SKIP),		// J_USB1
-				[7] = USB2_PORT_MID(OC_SKIP),		// Camera
-				[8] = USB2_PORT_MID(OC_SKIP),		// J_TYPEC1 (TBT)
-				[13] = USB2_PORT_MID(OC_SKIP),		// Bluetooth
-			}"
-			register "usb3_ports" = "{
-				[0] = USB3_PORT_DEFAULT(OC_SKIP),	// J_AUD1
-				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// J_USB1
-				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// J_TYPEC2
-			}"
-		end
-
-		device ref i2c0 on
-			# Touchpad I2C bus
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN0412""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""FTCS1000""
-				register "generic.desc" = ""FocalTech Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 38 on end
-			end
-		end
-		device ref i2c1 on
-			# Thunderbolt
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
-		end
-		device ref i2c2 on
-			# Pantone
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
-		end
-		device ref i2c3 on
-			# TAS5825M smart amp
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
-			chip drivers/i2c/tas5825m
-				register "id" = "0"
-				device i2c 4e on end # (8bit address: 0x9c)
-			end
-		end
-
-		device ref pcie5_0 on
-			# GPU
-			register "cpu_pcie_rp[CPU_RP(2)]" = "{
-				.clk_src = 14,
-				.clk_req = 14,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp3 on
-			# GLAN
-			register "pch_pcie_rp[PCH_RP(3)]" = "{
-				.clk_src = 13,
-				.clk_req = 13,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp5 on
-			# CARD
-			register "pch_pcie_rp[PCH_RP(5)]" = "{
-				.clk_src = 12,
-				.clk_req = 12,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG,
-			}"
-		end
-		device ref pcie_rp8 on
-			# WLAN
-			register "pch_pcie_rp[PCH_RP(8)]" = "{
-				.clk_src = 11,
-				.clk_req = 11,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp9 on
-			# SSD1
-			register "pch_pcie_rp[PCH_RP(9)]" = "{
-				.clk_src = 10,
-				.clk_req = 10,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp13 on
-			# SSD2
-			register "pch_pcie_rp[PCH_RP(13)]" = "{
-				.clk_src = 9,
-				.clk_req = 9,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end
-		device ref pcie_rp25 on
-			# TBT
-			# XXX: AER causes UnsupReq warnings
-			register "pch_pcie_rp[PCH_RP(25)]" = "{
-				.clk_src = 15,
-				.clk_req = 15,
-				.flags = PCIE_RP_LTR | PCIE_RP_HOTPLUG,
-			}"
-			chip drivers/intel/dtbt
-				device pci 00.0 on end
-			end
-		end
-	end
-end

src/mainboard/system76/rpl/variants/oryp12/romstage.c

@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/gfx/nvidia/gpu.h>
-#include <soc/meminit.h>
-#include <soc/romstage.h>
-#include <variant/gpio.h>
-
-void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
-	const struct mb_cfg board_cfg = {
-		.type = MEM_TYPE_DDR5,
-		.ect = true,
-		.LpDdrDqDqsReTraining = 1,
-		.ddr_config = {
-			.dq_pins_interleaved = true,
-		},
-	};
-	const struct mem_spd spd_info = {
-		.topo = MEM_TOPO_DIMM_MODULE,
-		.smbus = {
-			[0] = { .addr_dimm[0] = 0x50, },
-			[1] = { .addr_dimm[0] = 0x52, },
-		},
-	};
-	const bool half_populated = false;
-
-	const struct nvidia_gpu_config config = {
-		.power_gpio = DGPU_PWR_EN,
-		.reset_gpio = DGPU_RST_N,
-		.enable = true,
-	};
-
-	// Enable dGPU power
-	nvidia_set_power(&config);
-
-	// Set primary display to hybrid graphics
-	mupd->FspmConfig.PrimaryDisplay = 4;
-
-	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
-	mupd->FspmConfig.GpioOverride = 0;
-
-	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
-}

src/mainboard/system76/tgl-h/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/tgl-h/acpi/mainboard.asl

@@ -9,7 +9,6 @@
 Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
-		#include "backlight.asl"
 		Scope (PEG1) {
 			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
 		}

src/mainboard/system76/tgl-h/cmos.layout

@@ -14,10 +14,7 @@ entries
 412	4	e	6	debug_level
 416	1	e	2	me_state
 417	3	h	0	me_state_counter
-
+904	80	h	0	ramtop
-# CMOS_VSTART_ramtop
-800	80	r	0	ramtop
-
 984	16	h	0	check_sum
 
 enumerations
@@ -40,4 +37,4 @@ enumerations
 
 checksums
 
-checksum 408 799 984
+checksum 408 983 984

src/mainboard/system76/tgl-h/dsdt.asl

@@ -20,6 +20,7 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/tgl-u/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}