Intel® x86 coreboot/FSP Development Process

The x86 development process for coreboot is broken into the following components:

The development process has two main phases:

  1. Minimal coreboot; This phase is single threaded
  2. Adding coreboot features

Minimal coreboot

The combined steps below describe how to bring up a minimal coreboot for a system-on-a-chip (SoC) and a development board:

The initial coreboot steps are single threaded! The initial minimal FSP development is also single threaded. Progress can speed up by adding more developers after the minimal coreboot/FSP implementation reaches the payload.
  1. Get the necessary tools:
  2. Build the cross tools for i386:
  3. Get something to build:
    1. FSP 1.1 required files
    2. SoC required files
    3. Board required files
  4. Get result to start booting
  5. Early Debug
  6. Implement and debug the bootblock code
  7. Implement and debug the call to TempRamInit
  8. Enable the serial port
    1. Power on, enable and configure GPIOs for the debug serial UART
    2. Add the serial outupt support to romstage
  9. Enable coreboot/FSP debugging
  10. Determine the Previous Sleep State
  11. Enable DRAM:
    1. Implement the SoC MemoryInit Support
    2. Implement the board support to read the Memory Timing Data
  12. Disable the Shadow ROM
  13. Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration
  14. Implement the .init routine for the chip operations structure which calls FSP SiliconInit
  15. Start ramstage's device tree processing to display the PCI vendor and device IDs
  16. Disable the PCI devices
  17. Implement the memory map
  18. coreboot should now attempt to load the payload

Add coreboot Features

Most of the coreboot development gets done in this phase. Implementation tasks in this phase are easily done in parallel.

Features
SoC Where Testing
8254 Programmable Interval Timer Legacy hardware support CorebootPayloadPkg gets to shell prompt
8259 Programmable Interrupt Controller Legacy hardware support CorebootPayloadPkg gets to shell prompt
Cache-as-RAM Find FSP binary: cache_as_ram.inc
Enable: FSP 1.1 TempRamInit called from cache_as_ram.inc
Disable: FSP 1.1 TempRamExit called from after_raminit.S
 FindFSP: POST code 0x90 (POST_FSP_TEMP_RAM_INIT) is displayed
Enable: POST code 0x2A is displayed
Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
Memory Map Implement a device driver for the north cluster coreboot displays the memory map correctly during the BS_WRITE_TABLES state
MTRRs Set values: src/drivers/intel/fsp1_1/stack.c/setup_stack_and_mtrrs
Load values: src/drivers/intel/fsp1_1/after_raminit.S 		Set: Post code 0x91 (POST_FSP_TEMP_RAM_EXIT) is displayed by after_raminit.S
Load: Post code 0x3C is displayed by after_raminit.S
and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions
PCI Device Support Implement a PCI device driver The device is detected by coreboot and usable by the payload
Ramstage state machine Implement the chip and domain operations to start the device tree processing During the BS_DEV_ENUMERATE state, ramstage now display the device IDs for the PCI devices on the bus.
ROM Shadow
0x000E0000 - 0x000FFFFF		 Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/soc_after_ram_init routine Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written
Board Where Testing
Device Tree List PCI vendor and device IDs by starting the device tree processing
Disable PCI devices
Enable: Implement a PCI device driver 		List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs
Disable: BS_DEV_ENUMERATE state shows the devices as disabled
Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
DRAM Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/spd.c
UPD Setup: FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/raminit.c 		Select the following Kconfig values
  • DISPLAY_HOBS
  • DISPLAY_UPD_DATA
Testing successful if:
  • MemoryInit UPD values are correct
  • MemoryInit returns 0 (success) and
  • The the message "ERROR - coreboot's requirements not met by FSP binary!" is not displayed
Serial Port SoC Support
Enable: src/soc/mainboard/<Board>/com_init.c/car_mainboard_pre_console_init 		Debug serial output works
Payload Where Testing
ACPI Tables SoC Support
 Verified by payload or OS
FSP Where Testing
TempRamInit FSP TempRamInit FSP binary found: POST code 0x90 (POST_FSP_TEMP_RAM_INIT) is displayed
TempRamInit successful: POST code 0x2A is displayed
MemoryInit SoC support
Board support
 Select the following Kconfig values
  • DISPLAY_HOBS
  • DISPLAY_UPD_DATA
Testing successful if:
  • MemoryInit UPD values are correct
  • MemoryInit returns 0 (success) and
  • The the message "ERROR - coreboot's requirements not met by FSP binary!" is not displayed
TempRamExit src/drivers/intel/fsp1_1/after_raminit.S Post code 0x91 (POST_FSP_TEMP_RAM_EXIT) is displayed before calling TempRamExit by after_raminit.S, CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and Post code 0x39 is displayed by after_raminit.S
SiliconInit Implement the .init routine for the chip operations structure During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000
FspNotify The code which calls FspNotify is located in src/drivers/intel/fsp1_1/fsp_util.c. The fsp_notify_boot_state_callback routine is called three times as specified by the BOOT_STATE_INIT_ENTRY macros below the routine. The FspNotify routines are called during:
  • BS_DEV_RESOURCES - on exit
  • BS_PAYLOAD_LOAD - on exit
  • BS_OS_RESUME - on entry (S3 resume)

Modified: 4 March 2016