0949e73906
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
155 lines
4.7 KiB
ArmAsm
155 lines
4.7 KiB
ArmAsm
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Optimized assembly for low-level CPU operations on ARMv7 processors.
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*
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* Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD
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*/
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#include <arch/asm.h>
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#include <rules.h>
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/*
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* Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0]
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* bitfield in a register to the appropriate MCR instruction. This algorithm
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* works by initializing a bitfield with the highest-numbered set and way, and
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* generating a "set decrement" and a "way decrement". The former just contains
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* the LSB of the set field, but the latter contains the LSB of the way field
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* minus the highest valid set field... such that when you subtract it from a
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* [way:0:level] field you end up with a [way - 1:highest_set:level] field
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* through the magic of double subtraction. It's quite ingenious, really.
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* Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without
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* needing to write to memory.
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*
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* THIS FUNCTION MUST PRESERVE THE VALUE OF r10
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*/
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#if ENV_USER_SPACE
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/*
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* Empty macro for code running in userspace. Trying to manipulate the
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* cache from userspace hangs the system. To run code at a privileged level,
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* the userspace code needs to execute an API call to the privileged mode
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* code.
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*/
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.macro dcache_apply_all crm
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bx lr
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.endm
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#else
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.macro dcache_apply_all crm
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dsb
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mov r3, #-2 @ initialize level so that we start at 0
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1: @next_level
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add r3, r3, #2 @ increment level
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mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
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and ip, r0, #0x07000000 @ narrow to LoC
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lsr ip, ip, #23 @ left align LoC (low 4 bits)
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cmp r3, ip @ compare
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bge 3f @done @ else fall through (r0 == CLIDR)
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add r2, r3, r3, lsr #1 @ r2 = (level << 1) * 3 / 2
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mov r1, r0, lsr r2 @ r1 = cache type
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and r1, r1, #7
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cmp r1, #2 @ is it data or i&d?
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blt 1b @next_level @ nope, skip level
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mcr p15, 2, r3, c0, c0, 0 @ select cache level
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isb
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mrc p15, 1, r0, c0, c0, 0 @ read CCSIDR
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ubfx ip, r0, #0, #3 @ get linesize from CCSIDR
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add ip, ip, #4 @ apply bias
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ubfx r2, r0, #13, #15 @ get numsets - 1 from CCSIDR
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lsl r2, r2, ip @ shift to set position
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orr r3, r3, r2 @ merge set into way/set/level
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mov r1, #1
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lsl r1, r1, ip @ r1 = set decr
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ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
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clz r2, ip @ number of bits to MSB of way
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lsl ip, ip, r2 @ shift by that into way position
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mov r0, #1
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lsl r2, r0, r2 @ r2 now contains the way decr
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mov r0, r3 @ get sets/level (no way yet)
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orr r3, r3, ip @ merge way into way/set/level
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bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1
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sub r2, r2, r0 @ subtract from way decr
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/* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */
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2: mcr p15, 0, r3, c7, \crm, 2 @ writeback and/or invalidate line
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cmp r3, #15 @ are we done with this level (way/set == 0)
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bls 1b @next_level @ yes, go to next level
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lsr r0, r3, #4 @ clear level bits leaving only way/set bits
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lsls r0, r0, #14 @ clear way bits leaving only set bits
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subne r3, r3, r1 @ non-zero?, decrement set #
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subeq r3, r3, r2 @ zero?, decrement way # and restore set count
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b 2b
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3: @done
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mov r0, #0 @ default back to cache level 0
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mcr p15, 2, r0, c0, c0, 0 @ select cache level
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dsb
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isb
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bx lr
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.endm
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#endif /* ENV_USER_SPACE */
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/*
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* Bring an ARM processor we just gained control of (e.g. from IROM) into a
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* known state regarding caches/SCTLR. Completely cleans and invalidates
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* icache/dcache, disables MMU and dcache (if active), and enables unaligned
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* accesses, icache and branch prediction (if inactive). Clobbers r4 and r5.
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*
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* THIS FUNCTION MUST PRESERVE THE VALUE OF r10
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*/
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ENTRY(arm_init_caches)
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/* r4: SCTLR, return address: r5 (stay valid for the whole function) */
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mov r5, lr
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mrc p15, 0, r4, c1, c0, 0
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/* Activate ICache (12) and Branch Prediction (11) already for speed */
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orr r4, # (1 << 11) | (1 << 12)
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mcr p15, 0, r4, c1, c0, 0
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/* Flush and invalidate dcache in ascending order */
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bl dcache_invalidate_all
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#if ENV_ARMV7_A
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/* Deactivate MMU (0), Alignment Check (1) and DCache (2) */
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and r4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2)
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mcr p15, 0, r4, c1, c0, 0
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/* Invalidate icache and TLB for good measure */
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mcr p15, 0, r0, c7, c5, 0
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mcr p15, 0, r0, c8, c7, 0
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#endif
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#if ENV_ARMV7_R
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/* Deactivate Alignment Check (1) and DCache (2) */
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and r4, # ~(1 << 1) & ~(1 << 2)
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mcr p15, 0, r4, c1, c0, 0
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/* Invalidate icache for good measure */
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mcr p15, 0, r0, c7, c5, 0
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#endif
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dsb
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isb
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bx r5
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ENDPROC(arm_init_caches)
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ENTRY(dcache_invalidate_all)
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dcache_apply_all crm=c6
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ENDPROC(dcache_invalidate_all)
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ENTRY(dcache_clean_all)
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dcache_apply_all crm=c10
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ENDPROC(dcache_clean_all)
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ENTRY(dcache_clean_invalidate_all)
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dcache_apply_all crm=c14
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ENDPROC(dcache_clean_invalidate_all)
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