00b9f4c4b1
Changes the offsets of some options so that options that span multiple bytes are byte aligned. To make the cmos.layout file more consistent some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
149 lines
4.5 KiB
Plaintext
149 lines
4.5 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2007-2008 coresystems GmbH
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# 2012 secunet Security Networks AG
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; version 2 of
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# the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 240 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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392 3 e 5 baud_rate
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395 4 e 6 debug_level
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#399 1 r 0 unused
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 10 sata_mode
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409 2 e 7 power_on_after_fail
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# coreboot config options: EC
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411 1 e 9 first_battery
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412 1 e 1 bluetooth
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413 1 e 1 wwan
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414 1 e 1 wlan
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415 1 e 1 trackpoint
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416 8 h 0 volume
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424 1 e 1 fn_ctrl_swap
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425 1 e 1 sticky_fn
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426 1 e 1 power_management_beeps
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427 1 e 1 low_battery_beep
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428 1 e 1 uwb
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# coreboot config options: bootloader
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432 512 s 0 boot_devices
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944 8 h 0 boot_default
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# coreboot config options: northbridge
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952 2 e 12 hybrid_graphics_mode
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954 4 e 11 gfx_uma_size
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# coreboot config options: check sums
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984 16 h 0 check_sum
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#1000 24 r 0 unused
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# RAM initialization internal data
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1024 128 r 0 read_training_results
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 No
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8 1 Yes
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9 0 Secondary
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9 1 Primary
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10 0 AHCI
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10 1 Compatible
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11 0 1M
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11 1 4M
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11 2 8M
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11 3 16M
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11 4 32M
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11 5 48M
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11 6 64M
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11 7 128M
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11 8 256M
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11 9 96M
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11 10 160M
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11 11 224M
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11 12 352M
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12 0 Integrated Only
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12 1 Discrete Only
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12 2 Switchable
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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