aa969e887a
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
220 lines
4.8 KiB
Plaintext
220 lines
4.8 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Global Variables */
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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P80D, 32, // 0x0b - Debug port (IO 0x80) value
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LIDS, 8, // 0x0f - LID state (open = 1)
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, 8, // 0x10 - Power State (AC = 1)
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/* Thermal policy */
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Offset (0x11),
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TLVL, 8, // 0x11 - Throttle Level Limit
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FLVL, 8, // 0x12 - Current FAN Level
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TCRT, 8, // 0x13 - Critical Threshold
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TPSV, 8, // 0x14 - Passive Threshold
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TMAX, 8, // 0x15 - CPU Tj_max
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F0OF, 8, // 0x16 - FAN 0 OFF Threshold
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F0ON, 8, // 0x17 - FAN 0 ON Threshold
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F0PW, 8, // 0x18 - FAN 0 PWM value
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F1OF, 8, // 0x19 - FAN 1 OFF Threshold
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F1ON, 8, // 0x1a - FAN 1 ON Threshold
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F1PW, 8, // 0x1b - FAN 1 PWM value
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F2OF, 8, // 0x1c - FAN 2 OFF Threshold
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F2ON, 8, // 0x1d - FAN 2 ON Threshold
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F2PW, 8, // 0x1e - FAN 2 PWM value
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F3OF, 8, // 0x1f - FAN 3 OFF Threshold
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F3ON, 8, // 0x20 - FAN 3 ON Threshold
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F3PW, 8, // 0x21 - FAN 3 PWM value
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F4OF, 8, // 0x22 - FAN 4 OFF Threshold
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F4ON, 8, // 0x23 - FAN 4 ON Threshold
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F4PW, 8, // 0x24 - FAN 4 PWM value
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TMPS, 8, // 0x25 - Temperature Sensor ID
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/* Processor Identification */
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Offset (0x28),
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, 8, // 0x28 - Enabled by coreboot
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, 8, // 0x29 - Multi Processor Enable
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PCP0, 8, // 0x2a - PDC CPU/CORE 0
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PCP1, 8, // 0x2b - PDC CPU/CORE 1
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PPCM, 8, // 0x2c - Max. PPC state
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, 8, // 0x2d - Processor count
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/* Super I/O & CMOS config */
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Offset (0x32),
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NATP, 8, // 0x32 -
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S5U0, 8, // 0x33 - Enable USB0 in S5
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S5U1, 8, // 0x34 - Enable USB1 in S5
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S3U0, 8, // 0x35 - Enable USB0 in S3
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S3U1, 8, // 0x36 - Enable USB1 in S3
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S33G, 8, // 0x37 - Enable 3G in S3
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, 32, // 0x38 - CBMEM TOC
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/* Integrated Graphics Device */
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Offset (0x3c),
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IGDS, 8, // 0x3c - IGD state (primary = 1)
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TLST, 8, // 0x3d - Display Toggle List pointer
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CADL, 8, // 0x3e - Currently Attached Devices List
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PADL, 8, // 0x3f - Previously Attached Devices List
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/* Backlight Control */
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Offset (0x64),
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BLCS, 8, // 0x64 - Backlight control possible?
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BRTL, 8, // 0x65 - Brightness Level
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ODDS, 8, // 0x66
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/* Ambient Light Sensors */
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Offset (0x6e),
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ALSE, 8, // 0x6e - ALS enable
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ALAF, 8, // 0x6f - Ambient light adjustment factor
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LLOW, 8, // 0x70 - LUX Low
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LHIH, 8, // 0x71 - LUX High
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/* EMA */
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Offset (0x78),
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EMAE, 8, // 0x78 - EMA enable
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EMAP, 16, // 0x79 - EMA pointer
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EMAL, 16, // 0x7b - EMA length
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/* MEF */
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Offset (0x82),
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MEFE, 8, // 0x82 - MEF enable
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/* TPM support */
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Offset (0x8c),
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TPMP, 8, // 0x8c - TPM
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TPME, 8, // 0x8d - TPM enable
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/* SATA */
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Offset (0x96),
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GTF0, 56, // 0x96 - GTF task file buffer for port 0
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GTF1, 56, // 0x9d - GTF task file buffer for port 1
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GTF2, 56, // 0xa4 - GTF task file buffer for port 2
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IDEM, 8, // 0xab - IDE mode (compatible / enhanced)
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IDET, 8, // 0xac - IDE
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/* XHCI */
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Offset (0xb2),
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XHCI, 8,
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CBMC, 32,
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PM1I, 32, // System Wake Source - PM1 Index
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GPEI, 32, // GPE Wake Source
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}
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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Store (One, \S3U1)
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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Store (Zero, \S3U1)
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}
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/* Set flag to enable USB charging in S5 */
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Method (S5UE)
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{
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Store (One, \S5U0)
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Store (One, \S5U1)
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}
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/* Set flag to disable USB charging in S5 */
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Method (S5UD)
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{
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Store (Zero, \S5U0)
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Store (Zero, \S5U1)
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}
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/* Set flag to enable 3G module in S3 */
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Method (S3GE)
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{
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Store (One, \S33G)
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}
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/* Set flag to disable 3G module in S3 */
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Method (S3GD)
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{
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Store (Zero, \S33G)
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}
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/* Set XHCI Mode enable */
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Method (XHCE)
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{
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Store (One, \XHCI)
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}
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/* Set XHCI Mode disable */
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Method (XHCD)
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{
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Store (Zero, \XHCI)
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}
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External (\_TZ.SKIN)
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Method (TZUP)
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{
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#ifdef HAVE_THERMALZONE
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/* Update Primary Thermal Zone */
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If (CondRefOf (\_TZ.THRM)) {
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Notify (\_TZ.THRM, 0x81)
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}
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#endif
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/* Update Secondary Thermal Zone */
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If (CondRefOf (\_TZ.SKIN)) {
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Notify (\_TZ.SKIN, 0x81)
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}
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}
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/* Update Fan 0 thresholds */
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Method (F0UT, 2)
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{
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Store (Arg0, \F0OF)
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Store (Arg1, \F0ON)
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TZUP ()
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}
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/* Update Fan 1 thresholds */
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Method (F1UT, 2)
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{
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Store (Arg0, \F1OF)
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Store (Arg1, \F1ON)
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TZUP ()
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}
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/* Update Fan 2 thresholds */
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Method (F2UT, 2)
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{
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Store (Arg0, \F2OF)
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Store (Arg1, \F2ON)
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TZUP ()
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}
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/* Update Fan 3 thresholds */
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Method (F3UT, 2)
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{
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Store (Arg0, \F3OF)
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Store (Arg1, \F3ON)
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TZUP ()
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}
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/* Update Fan 4 thresholds */
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Method (F4UT, 2)
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{
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Store (Arg0, \F4OF)
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Store (Arg1, \F4ON)
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TZUP ()
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}
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/* Update Temperature Sensor ID */
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Method (TMPU, 1)
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{
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Store (Arg0, \TMPS)
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TZUP ()
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}
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