0142d441c6
It provides no useful information, so it might as well vanish. Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
64 lines
1.5 KiB
Plaintext
64 lines
1.5 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, /* DSDT revision: ACPI v2.0 and up */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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)
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{
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#include <acpi/platform.asl>
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/* global NVS and variables */
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#include <acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <acpi/southcluster.asl>
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#include <acpi/dptf/cpu.asl>
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#include <acpi/lpe.asl>
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}
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/* Dynamic Platform Thermal Framework */
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#include "acpi/dptf.asl"
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}
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Scope (\_SB.PCI0)
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{
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Device (RP03)
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{
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Name (_ADR, 0x001C0002) // _ADR: Address
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OperationRegion(RPXX, PCI_Config, 0x00, 0x10)
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/* Wifi Device */
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#include <soc/intel/common/acpi/wifi.asl>
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}
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}
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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#include "acpi/mainboard.asl"
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}
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