0210119b4b
Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3397 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
161 lines
3.6 KiB
Plaintext
161 lines
3.6 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/* Intel Cougar Point USB support */
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// EHCI Controller 0:1d.0
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Device (EHC1)
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{
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Name(_ADR, 0x001d0000)
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Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
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// Leave USB ports on for to allow Wake from USB
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Method(_S3D,0) // Highest D State in S3 State
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{
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Return (2)
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}
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Method(_S4D,0) // Highest D State in S4 State
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{
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Return (2)
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}
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Device (HUB7)
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{
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Name (_ADR, 0x00000000)
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// How many are there?
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Device (PRT1) { Name (_ADR, 1) } // USB Port 0
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Device (PRT2) { Name (_ADR, 2) } // USB Port 1
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Device (PRT3) { Name (_ADR, 3) } // USB Port 2
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Device (PRT4) { Name (_ADR, 4) } // USB Port 3
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Device (PRT5) { Name (_ADR, 5) } // USB Port 4
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Device (PRT6) { Name (_ADR, 6) } // USB Port 5
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}
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}
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// EHCI #2 Controller 0:1a.0
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Device (EHC2)
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{
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Name(_ADR, 0x001a0000)
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Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
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// Leave USB ports on for to allow Wake from USB
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Method(_S3D,0) // Highest D State in S3 State
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{
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Return (2)
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}
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Method(_S4D,0) // Highest D State in S4 State
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{
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Return (2)
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}
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Device (HUB7)
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{
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Name (_ADR, 0x00000000)
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// How many are there?
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Device (PRT1) { Name (_ADR, 1) } // USB Port 0
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Device (PRT2) { Name (_ADR, 2) } // USB Port 1
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Device (PRT3) { Name (_ADR, 3) } // USB Port 2
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Device (PRT4) { Name (_ADR, 4) } // USB Port 3
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Device (PRT5) { Name (_ADR, 5) } // USB Port 4
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Device (PRT6) { Name (_ADR, 6) } // USB Port 5
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}
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}
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Device (XHC)
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{
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Name(_ADR, 0x00140000)
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OperationRegion(XDEV, PCI_Config, 0, 256)
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Field(XDEV, DWordAcc, NoLock, Preserve)
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{
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Offset(0xD0),
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X2PR, 32, // XUSB2PR
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PRM2, 32, // XUSB2PRM
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SSEN, 32, // USB3_PSSEN
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RPM3, 32, // USB3PRM
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XPRT, 32, // XHCI Ports
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}
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Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
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Method(POSC,3,Serialized)
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{
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// Create DWord field from the Capabilities Buffer
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CreateDWordField(Arg2,0,CDW1)
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// Check revision
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If(LNotEqual(Arg1,One)) {
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// Set unknown revision bit
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Or(CDW1,0x8,CDW1)
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}
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// Set failure if xHCI is disabled by coreboot
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If(LEqual(XHCI, 0)) {
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Or(CDW1,0x2,CDW1)
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}
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// Query flag clear and xHCI in auto mode
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If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) {
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Store ("XHCI Switch", Debug)
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Store(Zero, Local0)
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And(XPRT, 0x3, Local0)
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If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) {
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Store(0xF, Local1)
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}
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ElseIf(LEqual(Local0, 2)) {
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Store(0x3, Local1)
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}
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ElseIf(LEqual(Local0, 3)) {
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Store(Zero, Local1)
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}
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And(RPM3, 0xFFFFFFF0, Local0)
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Or(Local0, Local1, RPM3)
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And(PRM2, 0xFFFFFFF0, Local0)
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Or(Local0, Local1, PRM2)
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And(SSEN, 0xFFFFFFF0, Local0)
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Or(Local0, Local1, SSEN)
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And(X2PR, 0xFFFFFFF0, Local0)
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Or(Local0, Local1, X2PR)
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}
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Return(Arg2)
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}
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// Leave USB ports on for to allow Wake from USB
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Method(_S3D,0) // Highest D State in S3 State
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{
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Return (2)
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}
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Method(_S4D,0) // Highest D State in S4 State
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{
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Return (2)
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}
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}
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