a2bc2540c2
Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
79 lines
1.5 KiB
ArmAsm
79 lines
1.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This path is for stages that are post bootblock. The gdt is reloaded
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* to accommodate platforms that are executing out of CAR. In order to
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* continue with C code execution one needs to set stack pointer and
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* clear .bss variables that are stage specific.
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*/
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#if CONFIG(RESET_VECTOR_IN_RAM)
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#define _STACK_TOP _eearlyram_stack
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#else
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#define _STACK_TOP _ecar_stack
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#endif
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#if ENV_X86_64
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.code64
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#else
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.code32
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#endif
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.section ".text._start", "ax", @progbits
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.global _start
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_start:
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/* Migrate GDT to this text segment */
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#if ENV_X86_64
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call gdt_init64
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#else
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call gdt_init
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#endif
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/* reset stack pointer to CAR/EARLYRAM stack */
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mov $_STACK_TOP, %esp
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#if ENV_SEPARATE_DATA_AND_BSS
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/* clear .bss section as it is not shared */
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cld
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xor %eax, %eax
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movl $(_ebss), %ecx
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movl $(_bss), %edi
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sub %edi, %ecx
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shrl $2, %ecx
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rep stosl
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/* Copy .data section content to Cache-As-Ram */
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movl $(_edata), %ecx
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movl $(_data), %edi
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sub %edi, %ecx
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shrl $2, %ecx
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movl $(_data_load),%esi
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rep movsl
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#endif
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#if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
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|| (ENV_SEPARATE_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
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/* Wait for a JTAG debugger to break in and set EBX non-zero */
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xor %ebx, %ebx
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debug_spinloop:
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cmp $0, %ebx
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jz debug_spinloop
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#endif
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andl $0xfffffff0, %esp
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#if CONFIG(IDT_IN_EVERY_STAGE)
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call exception_init
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#endif
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#if CONFIG(ASAN_IN_ROMSTAGE)
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call asan_init
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#endif
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call car_stage_entry
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/* Expect to never return. */
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1:
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jmp 1b
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