773485b892
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored and was not correctly set on affected sockets and boards. It was still referenced in romstage linker script. This was discovered by clang builds failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed. The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken from intel/cpu/cache_as_ram.inc. Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7887 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
21 lines
304 B
Plaintext
21 lines
304 B
Plaintext
config CPU_INTEL_SOCKET_MPGA479M
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bool
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select CPU_INTEL_MODEL_69X
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select CPU_INTEL_MODEL_6BX
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select CPU_INTEL_MODEL_6DX
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select CPU_INTEL_MODEL_F2X
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select MMX
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select SSE
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if CPU_INTEL_SOCKET_MPGA479M
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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endif
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