03784fa97a
This patch adds a new static assertion macro that can be used to check the offsets in structures that overlay register sets at compile time. It uses the _Static_assert() declaration from the new ISO C11 standard, which is supported (even without -std=c11) by GCC after version 4.6. (There is supposedly also support in clang, although I haven't tried it... let's deal with compiler issues when/if they turn up.) I've added it to all structures for our current ARM SoCs for now, and I think every new register overlay we add going forward should use them (at least for the last member, but feel free to add more if you think it's useful). Change-Id: If32510e7049739ad05618d363a854dc372d64386 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6905 Tested-by: build bot (Jenkins)
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA124_SYSCTR_H__
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#define __SOC_NVIDIA_TEGRA124_SYSCTR_H__
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#include <stdint.h>
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enum {
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SYSCTR_CNTCR_EN = 1 << 0,
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SYSCTR_CNTCR_HDBG = 1 << 1,
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SYSCTR_CNTCR_FCREQ = 1 << 8
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};
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struct sysctr_regs {
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uint32_t cntcr;
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uint32_t cntsr;
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uint32_t cntcv0;
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uint32_t cntcv1;
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uint8_t _rsv0[0x10];
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uint32_t cntfid0;
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uint32_t cntfid1;
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uint8_t _rsv1[0xfa8];
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uint32_t counterid4;
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uint32_t counterid5;
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uint32_t counterid6;
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uint32_t counterid7;
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uint32_t counterid0;
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uint32_t counterid1;
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uint32_t counterid2;
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uint32_t counterid3;
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uint32_t counterid8;
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uint32_t counterid9;
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uint32_t counterid10;
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uint32_t counterid11;
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};
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check_member(sysctr_regs, counterid11, 0xffc);
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#endif /* __SOC_NVIDIA_TEGRA124_SYSCTR_H__ */
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