038e7247dc
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
124 lines
3.3 KiB
ArmAsm
124 lines
3.3 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/asm.h>
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.arm
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/*
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* Just in case the maskrom or the vendor basic firmware passes on a
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* parameter when calling the bootblock, store it here for handling by C
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* code.
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*/
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.section .bss, "aw" @nobits
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.global maskrom_param
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.align 4
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maskrom_param:
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.word 0
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ENTRY(_start)
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/*
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* Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
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* aborts may happen early and crash before the abort handlers are
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* installed, but at least the problem will show up near the code that
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* causes it.
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*/
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msr cpsr_cxf, #0xdf
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bl _thumb_start
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ENDPROC(_start)
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.thumb
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ENTRY(_thumb_start)
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/* Preserve the maskrom passed value, if any */
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mov r10, r0
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/* Disable L2 Cache */
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ldr r1, =0x0
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ldr r0, =0xD0008100
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str r1, [r0]
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/* Disable windows that overlap with 0xF1000000 */
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/* By default, window #12 overlaps with 0xF1000000 */
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mov r1, #0
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ldr r0, =0xD00200B0
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str r1, [r0]
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/* Set Registers Base address. */
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ldr r1, =0xf1000000
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ldr r0, =0xD0020080
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str r1, [r0]
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/* Update SCU (peripheral) register Base address with
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* correct INTER_REG_BASE
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*/
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ldr r2, = 0xC000 /* SCU offset = 0xC000 */
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add r1, r1, r2 /* r1 = INTER_REG_BASE + SCU_OFFSET */
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mcr p15, 4, r1, c15, c0, 0 /* Write SCU base register */
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bl arm_init_caches
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/*
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* From Cortex-A Series Programmer's Guide:
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* Only CPU 0 performs initialization. Other CPUs go into WFI
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* to do this, first work out which CPU this is
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* this code typically is run before any other initialization step
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*/
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mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register
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and r1, r1, #0x3 @ Extract CPU ID bits
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cmp r1, #0
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bne wait_for_interrupt @ If this is not core0, wait
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/*
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* Initialize the stack to a known value. This is used to check for
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* stack overflow later in the boot process.
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*/
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ldr r0, =_stack
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ldr r1, =_estack
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ldr r2, =0xdeadbeef
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init_stack_loop:
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str r2, [r0]
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add r0, #4
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cmp r0, r1
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bne init_stack_loop
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ldr r0, =_bss
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ldr r1, =_ebss
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mov r2, #0x00000000 /* prepare zero to clear BSS */
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clbss_l:
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str r2, [r0]
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add r0, #4
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cmp r0, r1
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bne clbss_l
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call_bootblock:
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/* Restore parameter passed in by maskrom/vendor firmware. */
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ldr r0, =maskrom_param
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str r10, [r0]
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/* Set stackpointer in internal RAM to call bootblock main() */
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ldr sp, =_estack
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ldr r0,=0x00000000
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/*
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* The current design of cpu_info places the struct at the top of the
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* stack. Free enough space to accommodate for that, but make sure it's
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* 8-byte aligned for ABI compliance.
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*/
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sub sp, sp, #16
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bl main
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wait_for_interrupt:
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wfi
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mov pc, lr @ back to my caller
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ENDPROC(_thumb_start)
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