042f0430d3
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
106 lines
2.7 KiB
C
106 lines
2.7 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
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#include "southbridge/amd/cs5535/cs5535_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/gx2/raminit.h"
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static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
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msr_t msr;
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/* 1. Initialize GLMC registers base on SPD values,
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* Hard coded as XpressROM for now */
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//print_debug("sdram_enable step 1\r\n");
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msr = rdmsr(0x20000018);
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msr.hi = 0x10076013;
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msr.lo = 0x00003000;
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wrmsr(0x20000018, msr);
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msr = rdmsr(0x20000019);
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msr.hi = 0x18000108;
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msr.lo = 0x696332a3;
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wrmsr(0x20000019, msr);
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}
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#include "northbridge/amd/gx2/raminit.c"
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#include "sdram/generic_sdram.c"
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#define PLLMSRhi 0x00001490
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#define PLLMSRlo 0x02000030
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#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
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#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
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#include "northbridge/amd/gx2/pll_reset.c"
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static void msr_init(void)
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{
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__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
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__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
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__builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
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__builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
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__builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
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__builtin_wrmsr(0x10000080, 0x3, 0x0);
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__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
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__builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
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__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
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__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
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__builtin_wrmsr(0x50002001, 0x27, 0x0);
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__builtin_wrmsr(0x4c002001, 0x1, 0x0);
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}
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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};
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msr_init();
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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cs5535_early_setup();
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pll_reset();
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/* Halt if there was a built in self test failure */
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//report_bist_failure(bist);
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sdram_initialize(1, memctrl);
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/* Check all of memory */
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ram_check(0x00000000, 640*1024);
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}
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