043eb0e35f
This patch unfortunately incorporates a number of changes, all of which are making future ARM ports easier. - drop cruft that came in with u-boot - move serial console from mainboard Kconfig to Exynos Kconfig - factor out non-board specific wakeup code - move generic bootblock code from mainboard to Exynos - actually call arch_cpu_init() - remove dead code - fix up copyright messages - remove snow_ prefix from a lot of code to reduce the noise when creating a new mainboard based on that code. Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3640 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
138 lines
2.8 KiB
Plaintext
138 lines
2.8 KiB
Plaintext
config BOOTBLOCK_CPU_INIT
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string
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default "cpu/samsung/exynos5250/bootblock.c"
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help
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CPU/SoC-specific bootblock code. This is useful if the
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bootblock must load microcode or copy data from ROM before
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searching for the bootblock.
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config EXYNOS_ACE_SHA
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bool
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default n
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config SATA_AHCI
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bool
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default n
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config BL1_SIZE_KB
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int
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default 8
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# Example SRAM/iRAM map for Exynos5250 platform:
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#
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# 0x0202_0000: vendor-provided BL1
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# 0x0202_3400: bootblock, assume up to 32KB in size
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# 0x0203_0000: romstage, assume up to 128KB in size.
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# 0x0207_8000: stack pointer
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config BOOTBLOCK_BASE
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hex
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default 0x02023400
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config ROMSTAGE_BASE
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hex
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default 0x02030000
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config ROMSTAGE_SIZE
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hex
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default 0x10000
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# Stack may reside in either IRAM or DRAM. We will define it to live
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# at the top of IRAM for now.
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#
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# Stack grows downward, push operation stores register contents in
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# consecutive memory locations ending just below SP
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config STACK_TOP
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hex
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default 0x02078000
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config STACK_BOTTOM
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hex
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default 0x02077000
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config STACK_SIZE
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hex
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default 0x1000
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config CBFS_ROM_OFFSET
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# Calculated by BL1 + max bootblock size.
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hex "offset of CBFS data in ROM"
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default 0x0A000
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# TODO Change this to some better address not overlapping bootblock when
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# cbfstool supports creating header in arbitrary location.
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x2040
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# TODO We may probably move this to board-specific implementation files instead
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# of KConfig values.
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x02060000
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x000017000
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# FIXME: This is for copying SPI content into SRAM temporarily and
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# will be removed when we have the SPI streaming driver implemented.
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config SPI_IMAGE_HACK
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hex
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default 0x02060000
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# FIXME: other magic numbers that should probably go away
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config XIP_ROM_SIZE
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hex
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default ROMSTAGE_SIZE
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config SYS_SDRAM_BASE
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hex
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default 0x40000000
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config SYS_TEXT_BASE
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hex
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default 0x43e00000
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config COREBOOT_TABLES_SIZE
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hex
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default 0x4000000
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choice CONSOLE_SERIAL_UART_CHOICES
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prompt "Serial Console UART"
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default CONSOLE_SERIAL_UART3
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depends on CONSOLE_SERIAL_UART
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config CONSOLE_SERIAL_UART0
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bool "UART0"
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help
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Serial console on UART0
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config CONSOLE_SERIAL_UART1
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bool "UART1"
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help
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Serial console on UART1
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config CONSOLE_SERIAL_UART2
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bool "UART2"
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help
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Serial console on UART2
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config CONSOLE_SERIAL_UART3
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bool "UART3"
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help
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Serial console on UART3
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endchoice
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config CONSOLE_SERIAL_UART_ADDRESS
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hex
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depends on CONSOLE_SERIAL_UART
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default 0x12c00000 if CONSOLE_SERIAL_UART0
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default 0x12c10000 if CONSOLE_SERIAL_UART1
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default 0x12c20000 if CONSOLE_SERIAL_UART2
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default 0x12c30000 if CONSOLE_SERIAL_UART3
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help
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Map the UART names to the respective MMIO address.
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