0461005908
Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
66 lines
1.1 KiB
Plaintext
66 lines
1.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
|
|
config NORTHBRIDGE_INTEL_IRONLAKE
|
|
bool
|
|
select CPU_INTEL_MODEL_2065X
|
|
select VGA
|
|
select INTEL_EDID
|
|
select INTEL_GMA_ACPI
|
|
select CACHE_MRC_SETTINGS
|
|
select HAVE_DEBUG_RAM_SETUP
|
|
select NO_DDR5
|
|
select NO_LPDDR4
|
|
select NO_DDR4
|
|
select NO_DDR2
|
|
select USE_DDR3
|
|
|
|
if NORTHBRIDGE_INTEL_IRONLAKE
|
|
|
|
config VBOOT
|
|
select VBOOT_MUST_REQUEST_DISPLAY
|
|
select VBOOT_STARTS_IN_BOOTBLOCK
|
|
# CPU is reset without platform/TPM during romstage
|
|
select TPM_STARTUP_IGNORE_POSTINIT
|
|
|
|
config CBFS_SIZE
|
|
default 0x100000
|
|
|
|
config VGA_BIOS_ID
|
|
string
|
|
default "8086,0046"
|
|
|
|
config DCACHE_RAM_BASE
|
|
hex
|
|
default 0xfefc0000
|
|
|
|
config DCACHE_RAM_SIZE
|
|
hex
|
|
default 0x10000
|
|
|
|
config DCACHE_BSP_STACK_SIZE
|
|
hex
|
|
default 0x2000
|
|
help
|
|
The amount of anticipated stack usage in CAR by bootblock and
|
|
other stages.
|
|
|
|
config ECAM_MMCONF_BASE_ADDRESS
|
|
default 0xe0000000
|
|
|
|
config ECAM_MMCONF_BUS_NUMBER
|
|
default 256
|
|
|
|
config INTEL_GMA_BCLV_OFFSET
|
|
default 0x48254
|
|
|
|
config FIXED_MCHBAR_MMIO_BASE
|
|
default 0xfed10000
|
|
|
|
config FIXED_DMIBAR_MMIO_BASE
|
|
default 0xfed18000
|
|
|
|
config FIXED_EPBAR_MMIO_BASE
|
|
default 0xfed19000
|
|
|
|
endif
|