04c06005eb
- Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[]. - Refine some names and macros. - Clean up some whitespace errors. - Add IDs and names of 5, 6 and 7 Series southbridges and the three latest Core CPU families with integrated memory controllers but do not implement any pretty printing routines for them yet. The first generation Core family is already supported, although it was wrongly named after the PCH and used the wrong ID. Also, the BAR values have been mangled to 32b instead of 64b. Both errors have been fixed and most basic support for the other two generations was added. Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1574 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
351 lines
11 KiB
C
351 lines
11 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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* Copyright (C) 2012 Anton Kochkov
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include "inteltool.h"
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static const io_register_t sandybridge_dmi_registers[] = {
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{ 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability
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{ 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1
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{ 0x08, 4, "DMI PVVAP2" }, // DMI Port VC Capability Register 2
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{ 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
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/* { 0x0E, 2, "RSVD" }, // Reserved */
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{ 0x10, 4, "DMI VC0RCAP" }, // DMI VC0 Resource Capability
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{ 0x14, 4, "DMI VC0RCTL" }, // DMI VC0 Resource Control
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/* { 0x18, 2, "RSVD" }, // Reserved */
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{ 0x1A, 2, "DMI VC0RSTS" }, // DMI VC0 Resource Status
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{ 0x1C, 4, "DMI VC1RCAP" }, // DMI VC1 Resource Capability
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{ 0x20, 4, "DMI VC1RCTL" }, // DMI VC1 Resource Control
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/* { 0x24, 2, "RSVD" }, // Reserved */
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{ 0x26, 2, "DMI VC1RSTS" }, // DMI VC1 Resource Status
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{ 0x28, 4, "DMI VCPRCAP" }, // DMI VCp Resource Capability
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{ 0x2C, 4, "DMI VCPRCTL" }, // DMI VCp Resource Control
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/* { 0x30, 2, "RSVD" }, // Reserved */
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{ 0x32, 2, "DMI VCPRSTS" }, // DMI VCp Resource Status
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{ 0x34, 4, "DMI VCMRCAP" }, // DMI VCm Resource Capability
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{ 0x38, 4, "DMI VCMRCTL" }, // DMI VCm Resource Control
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/* { 0x3C, 2, "RSVD" }, // Reserved */
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{ 0x3E, 2, "DMI VCMRSTS" }, // DMI VCm Resource Status
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/* { 0x40, 4, "RSVD" }, // Reserved */
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{ 0x44, 4, "DMI ESC" }, // DMI Element Self Description
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/* { 0x48, 8, "RSVD" }, // Reserved */
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{ 0x50, 4, "DMI LE1D" }, // DMI Link Entry 1 Description
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/* { 0x54, 4, "RSVD" }, // Reserved */
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{ 0x58, 4, "DMI LE1A" }, // DMI Link Entry 1 Address
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{ 0x5C, 4, "DMI LUE1A" }, // DMI Link Upper Entry 1 Address
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{ 0x60, 4, "DMI LE2D" }, // DMI Link Entry 2 Description
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/* { 0x64, 4, "RSVD" }, // Reserved */
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{ 0x68, 4, "DMI LE2A" }, // DMI Link Entry 2 Address
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/* { 0x6C, 4, "RSVD" }, // Reserved
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{ 0x70, 8, "RSVD" }, // Reserved
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{ 0x78, 8, "RSVD" }, // Reserved
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{ 0x80, 4, "RSVD" }, // Reserved */
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{ 0x84, 4, "LCAP" }, // Link Capabilities
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{ 0x88, 2, "LCTL" }, // Link Control
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{ 0x8A, 2, "LSTS" }, // Link Status
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/* { 0x8C, 4, "RSVD" }, // Reserved
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{ 0x90, 4, "RSVD" }, // Reserved
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{ 0x94, 4, "RSVD" }, // Reserved */
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{ 0x98, 2, "LCTL2" }, // Link Control 2
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{ 0x9A, 2, "LSTS2" }, // Link Status 2
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/* ... - Reserved */
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{ 0xBC0, 4, "AFE_BMUF0" }, // AFE BMU Configuration Function 0
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{ 0xBC4, 4, "RSVD" }, // Reserved
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{ 0xBC8, 4, "RSVD" }, // Reserved
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{ 0xBCC, 4, "AFE_BMUT0" }, // AFE BMU Configuration Test 0
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/* ... - Reserved */
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};
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/*
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* Egress Port Root Complex MMIO configuration space
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*/
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int print_epbar(struct pci_dev *nb)
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{
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int i, size = (4 * 1024);
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volatile uint8_t *epbar;
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uint64_t epbar_phys;
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printf("\n============= EPBAR =============\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82915:
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case PCI_DEVICE_ID_INTEL_82945GM:
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case PCI_DEVICE_ID_INTEL_82945GSE:
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case PCI_DEVICE_ID_INTEL_82945P:
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case PCI_DEVICE_ID_INTEL_82975X:
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_82965PM:
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case PCI_DEVICE_ID_INTEL_82Q965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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case PCI_DEVICE_ID_INTEL_82X38:
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case PCI_DEVICE_ID_INTEL_32X0:
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case PCI_DEVICE_ID_INTEL_82X4X:
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case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
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case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810_DC:
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case PCI_DEVICE_ID_INTEL_82810E_DC:
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case PCI_DEVICE_ID_INTEL_82830M:
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case PCI_DEVICE_ID_INTEL_82865:
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printf("This northbridge does not have EPBAR.\n");
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return 1;
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default:
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printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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epbar = map_physical(epbar_phys, size);
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if (epbar == NULL) {
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perror("Error mapping EPBAR");
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exit(1);
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}
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printf("EPBAR = 0x%08" PRIx64 " (MEM)\n\n", epbar_phys);
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(epbar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
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}
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unmap_physical((void *)epbar, size);
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return 0;
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}
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/*
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* MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
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*/
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int print_dmibar(struct pci_dev *nb)
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{
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int i, size = (4 * 1024);
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volatile uint8_t *dmibar;
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uint64_t dmibar_phys;
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const io_register_t *dmi_registers = NULL;
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printf("\n============= DMIBAR ============\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82915:
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case PCI_DEVICE_ID_INTEL_82945GM:
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case PCI_DEVICE_ID_INTEL_82945GSE:
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case PCI_DEVICE_ID_INTEL_82945P:
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case PCI_DEVICE_ID_INTEL_82975X:
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dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_82965PM:
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case PCI_DEVICE_ID_INTEL_82Q965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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case PCI_DEVICE_ID_INTEL_82X38:
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case PCI_DEVICE_ID_INTEL_32X0:
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case PCI_DEVICE_ID_INTEL_82X4X:
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case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
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case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
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dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
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dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810_DC:
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case PCI_DEVICE_ID_INTEL_82810E_DC:
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case PCI_DEVICE_ID_INTEL_82865:
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printf("This northbridge does not have DMIBAR.\n");
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return 1;
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case PCI_DEVICE_ID_INTEL_82X58:
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dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
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break;
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case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
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dmibar_phys = pci_read_long(nb, 0x68);
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dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
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dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */
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dmi_registers = NULL; /* No public documentation */
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break;
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
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dmi_registers = sandybridge_dmi_registers;
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size = ARRAY_SIZE(sandybridge_dmi_registers);
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
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dmibar_phys = pci_read_long(nb, 0x68);
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dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
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dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
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break;
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default:
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printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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dmibar = map_physical(dmibar_phys, size);
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if (dmibar == NULL) {
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perror("Error mapping DMIBAR");
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exit(1);
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}
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printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys);
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if (dmi_registers != NULL) {
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for (i = 0; i < size; i++) {
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switch (dmi_registers[i].size) {
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case 4:
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printf("dmibase+0x%04x: 0x%08x (%s)\n",
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dmi_registers[i].addr,
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*(uint32_t *)(dmibar+dmi_registers[i].addr),
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dmi_registers[i].name);
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break;
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case 2:
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printf("dmibase+0x%04x: 0x%04x (%s)\n",
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dmi_registers[i].addr,
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*(uint16_t *)(dmibar+dmi_registers[i].addr),
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dmi_registers[i].name);
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break;
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case 1:
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printf("dmibase+0x%04x: 0x%02x (%s)\n",
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dmi_registers[i].addr,
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*(uint8_t *)(dmibar+dmi_registers[i].addr),
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dmi_registers[i].name);
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break;
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}
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}
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} else {
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(dmibar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
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}
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}
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unmap_physical((void *)dmibar, size);
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return 0;
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}
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/*
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* PCIe MMIO configuration space
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*/
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int print_pciexbar(struct pci_dev *nb)
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{
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uint64_t pciexbar_reg;
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uint64_t pciexbar_phys;
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volatile uint8_t *pciexbar;
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int max_busses, devbase, i;
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int bus, dev, fn;
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printf("========= PCIEXBAR ========\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82915:
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case PCI_DEVICE_ID_INTEL_82945GM:
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case PCI_DEVICE_ID_INTEL_82945GSE:
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case PCI_DEVICE_ID_INTEL_82945P:
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case PCI_DEVICE_ID_INTEL_82975X:
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pciexbar_reg = pci_read_long(nb, 0x48);
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break;
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case PCI_DEVICE_ID_INTEL_82965PM:
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case PCI_DEVICE_ID_INTEL_82Q965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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case PCI_DEVICE_ID_INTEL_82X38:
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case PCI_DEVICE_ID_INTEL_32X0:
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case PCI_DEVICE_ID_INTEL_82X4X:
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case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
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case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
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pciexbar_reg = pci_read_long(nb, 0x60);
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pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810_DC:
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case PCI_DEVICE_ID_INTEL_82810E_DC:
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case PCI_DEVICE_ID_INTEL_82865:
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printf("Error: This northbridge does not have PCIEXBAR.\n");
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return 1;
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default:
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printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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if (!(pciexbar_reg & (1 << 0))) {
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printf("PCIEXBAR register is disabled.\n");
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return 0;
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}
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: // 256MB
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pciexbar_phys = pciexbar_reg & (0xff << 28);
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max_busses = 256;
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break;
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case 1: // 128M
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pciexbar_phys = pciexbar_reg & (0x1ff << 27);
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max_busses = 128;
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break;
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case 2: // 64M
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pciexbar_phys = pciexbar_reg & (0x3ff << 26);
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max_busses = 64;
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break;
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default: // RSVD
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printf("Undefined address base. Bailing out.\n");
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return 1;
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}
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printf("PCIEXBAR: 0x%08" PRIx64 "\n", pciexbar_phys);
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pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
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if (pciexbar == NULL) {
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perror("Error mapping PCIEXBAR");
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exit(1);
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}
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for (bus = 0; bus < max_busses; bus++) {
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for (dev = 0; dev < 32; dev++) {
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for (fn = 0; fn < 8; fn++) {
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devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
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if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
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continue;
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/* This is a heuristics. Anyone got a better check? */
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if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
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(*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
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#if DEBUG
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printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
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#endif
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continue;
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}
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printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
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for (i = 0; i < 4096; i++) {
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if((i % 0x10) == 0)
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printf("\n%04x:", i);
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printf(" %02x", *(pciexbar+devbase+i));
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}
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printf("\n");
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}
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}
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}
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unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));
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return 0;
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}
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