f17519120a
The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: I29bc17488539dbe695908e47f0b80c07e102e17d Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/3666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
261 lines
6.1 KiB
C
261 lines
6.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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* Copyright (C) 2012 Samsung Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Header file for Samsung DP (Display Port) interface driver. */
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#ifndef CPU_SAMSUNG_EXYNOS5420_DP_CORE_H
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#define CPU_SAMSUNG_EXYNOS5420_DP_CORE_H
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#define STREAM_ON_TIMEOUT 100
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#define PLL_LOCK_TIMEOUT 10
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#define DP_INIT_TRIES 10
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#define MAX_CR_LOOP 5
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#define MAX_EQ_LOOP 4
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/* Link tare type */
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enum link_rate {
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LINK_RATE_1_62GBPS = 0x06,
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LINK_RATE_2_70GBPS = 0x0a
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};
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/* Number of lanes supported */
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enum link_lane_count {
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LANE_COUNT1 = 1,
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LANE_COUNT2 = 2,
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LANE_COUNT4 = 4
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};
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/* Pre emphasis level */
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enum pre_emphasis_level {
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PRE_EMPHASIS_LEVEL_0,
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PRE_EMPHASIS_LEVEL_1,
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PRE_EMPHASIS_LEVEL_2,
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PRE_EMPHASIS_LEVEL_3,
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};
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/* Type of color space */
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enum color_space {
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COLOR_RGB,
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COLOR_YCBCR422,
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COLOR_YCBCR444
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};
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/* Video input Bit Per Color */
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enum color_depth {
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COLOR_6,
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COLOR_8,
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COLOR_10,
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COLOR_12
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};
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/* Type of YCbCr coefficient */
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enum color_coefficient {
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COLOR_YCBCR601,
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COLOR_YCBCR709
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};
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/* Color range */
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enum dynamic_range {
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VESA,
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CEA
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};
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/* Status of PLL clock */
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enum pll_status {
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PLL_UNLOCKED,
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PLL_LOCKED
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};
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/* To choose type of m_value */
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enum clock_recovery_m_value_type {
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CALCULATED_M,
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REGISTER_M
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};
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struct video_info {
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enum color_space color_space;
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enum dynamic_range dynamic_range;
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enum color_coefficient ycbcr_coeff;
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enum color_depth color_depth;
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enum link_rate link_rate;
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enum link_lane_count lane_count;
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char *name;
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unsigned int h_sync_polarity:1;
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unsigned int v_sync_polarity:1;
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unsigned int interlaced:1;
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};
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struct link_train {
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u8 link_rate;
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u8 lane_count;
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};
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struct s5p_dp_device {
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unsigned int irq;
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struct exynos5_dp *base;
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struct video_info *video_info;
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struct link_train link_train;
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};
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/* s5p_dp_reg.c */
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/*
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* Reset DP module
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*
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* param dp pointer to main s5p-dp structure
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*/
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void s5p_dp_reset(struct s5p_dp_device *dp);
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/*
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* Initialize DP to recieve video stream
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*
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* param dp pointer to main s5p-dp structure
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*/
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void s5p_dp_init_video(struct s5p_dp_device *dp);
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/*
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* Check whether PLL is locked
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*
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* param dp pointer to main s5p-dp structure
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* return Lock status
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*/
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unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp);
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/*
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* Initialize analog functions of DP
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*
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* param dp pointer to main s5p-dp structure
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* return 0 on success
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*/
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int s5p_dp_init_analog_func(struct s5p_dp_device *dp);
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/*
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* Initialize DP for AUX transaction
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*
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* param dp pointer to main s5p-dp structure
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*/
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void s5p_dp_init_aux(struct s5p_dp_device *dp);
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/*
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* Start an AUX transaction.
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*
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* param dp pointer to main s5p-dp structure
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*/
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int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp);
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/*
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* Write a byte to DPCD register
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*
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* param dp pointer to main s5p-dp structure
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* param reg_addr DPCD register to be written
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* param data byte data to be written
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* return write status
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*/
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int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
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unsigned int reg_addr,
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unsigned char data);
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/*
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* Read a byte from DPCD register
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*
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* param dp pointer to main s5p-dp structure
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* param reg_addr DPCD register to read
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* param data read byte data
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* return read status
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*/
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int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
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unsigned int reg_addr,
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unsigned char *data);
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/*
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* Initialize DP video functions
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*
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* param dp pointer to main s5p-dp structure
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*/
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//void s5p_dp_init_video(struct s5p_dp_device *dp);
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/*
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* Set color parameters for display
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*
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* param dp pointer to main s5p-dp structure
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* param color_depth Video input Bit Per Color
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* param color_space Colorimetric format of input video
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* param dynamic_range VESA range or CEA range
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* param coeff YCbCr Coefficients of input video
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*/
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void s5p_dp_set_video_color_format(struct s5p_dp_device *dp,
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unsigned int color_depth,
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unsigned int color_space,
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unsigned int dynamic_range,
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unsigned int coeff);
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/*
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* Check whether video clock is on
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*
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* param dp pointer to main s5p-dp structure
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* return clock status
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*/
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int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp);
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/*
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* Check whether video clock is on
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*
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* param dp pointer to main s5p-dp structure
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* param type clock_recovery_m_value_type
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* param m_value to caluculate m_vid value
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* param n_value to caluculate n_vid value
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*/
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void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp,
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enum clock_recovery_m_value_type type,
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unsigned int m_value,
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unsigned int n_value);
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/*
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* Set DP to video slave mode thereby enabling video master
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*
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* param dp pointer to main s5p-dp structure
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*/
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void s5p_dp_enable_video_master(struct s5p_dp_device *dp);
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/*
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* Check whether video stream is on
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*
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* param dp pointer to main s5p-dp structure
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* return video stream status
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*/
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int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp);
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/*
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* Configure DP in slave mode
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*
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* param dp pointer to main s5p-dp structure
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* param video_info pointer to main video_info structure.
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*/
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void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
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struct video_info *video_info);
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/*
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* Wait unitl HW link training done
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*
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* param dp pointer to main s5p-dp structure
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*/
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void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
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/* startup and init */
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struct exynos5_fimd_panel;
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void fb_init(unsigned long int fb_size, void *lcdbase,
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struct exynos5_fimd_panel *pd);
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int dp_controller_init(struct s5p_dp_device *dp_device);
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int lcd_ctrl_init(unsigned long int fb_size,
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struct exynos5_fimd_panel *panel_data, void *lcdbase);
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#endif /* CPU_SAMSUNG_EXYNOS5420_DP_CORE_H */
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