053bd0753b
Populate the PCI mmio region from NVS TOLM variable. Other regions are fixed. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Iec8352b0464ad850a76bd1706c028628c477731d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175628 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4938 Tested-by: build bot (Jenkins)
196 lines
6.0 KiB
Plaintext
196 lines
6.0 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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Scope(\)
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{
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// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
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OperationRegion(IO_T, SystemIO, 0x800, 0x10)
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Field(IO_T, ByteAcc, NoLock, Preserve)
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{
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Offset(0x8),
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TRP0, 8 // IO-Trap at 0x808
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}
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}
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Name(_HID,EISAID("PNP0A08")) // PCIe
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Name(_CID,EISAID("PNP0A03")) // PCI
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Name(_ADR, 0)
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Name(_BBN, 0)
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Method (_CRS, 0, Serialized)
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{
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Name (MCRS, ResourceTemplate()
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{
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// Bus Numbers
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
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// IO Region 0
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
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// PCI Config Space
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Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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// IO Region 1
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
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// VGA memory (0xa0000-0xbffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
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0x00020000,,, ASEG)
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// OPROM reserved (0xc0000-0xc3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
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0x00004000,,, OPR0)
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// OPROM reserved (0xc4000-0xc7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
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0x00004000,,, OPR1)
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// OPROM reserved (0xc8000-0xcbfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
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0x00004000,,, OPR2)
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// OPROM reserved (0xcc000-0xcffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
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0x00004000,,, OPR3)
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// OPROM reserved (0xd0000-0xd3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
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0x00004000,,, OPR4)
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// OPROM reserved (0xd4000-0xd7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
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0x00004000,,, OPR5)
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// OPROM reserved (0xd8000-0xdbfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
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0x00004000,,, OPR6)
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// OPROM reserved (0xdc000-0xdffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
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0x00004000,,, OPR7)
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// BIOS Extension (0xe0000-0xe3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
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0x00004000,,, ESG0)
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// BIOS Extension (0xe4000-0xe7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
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0x00004000,,, ESG1)
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// BIOS Extension (0xe8000-0xebfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
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0x00004000,,, ESG2)
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// BIOS Extension (0xec000-0xeffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ec000, 0x000effff, 0x00000000,
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0x00004000,,, ESG3)
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// System BIOS (0xf0000-0xfffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
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0x00010000,,, FSEG)
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// PCI Memory Region (Top of memory-0xfeafffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x00000000, 0xfeafffff, 0x00000000,
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0xfeb00000,,, PMEM)
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// TPM Area (0xfed40000-0xfed44fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
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0x00005000,,, TPMR)
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})
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// Update PCI resource area
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CreateDwordField(MCRS, PMEM._MIN, PMIN)
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CreateDwordField(MCRS, PMEM._MAX, PMAX)
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CreateDwordField(MCRS, PMEM._LEN, PLEN)
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// TOLM is BMBOUND accessible from IOSF so is saved in NVS
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Store (\TOLM, PMIN)
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Add (Subtract (PMAX, PMIN), 1, PLEN)
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Return (MCRS)
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}
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/* Device Resource Consumption */
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Device (PDRC)
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{
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Name (_HID, EISAID("PNP0C02"))
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Name (_UID, 1)
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Name (PDRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
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Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
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Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
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Memory32Fixed(ReadWrite, IO_BASE_ADDRESS, IO_BASE_SIZE)
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Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
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Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
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Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
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Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
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Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
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#if CONFIG_CHROMEOS_RAMOOPS
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Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
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CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
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#endif
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})
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// Current Resource Settings
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Method (_CRS, 0, Serialized)
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{
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Return(PDRS)
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}
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}
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