Furquan Shaikh 05a6f29d32 soc/intel/skylake: Add support for GSPI controller ...

Sky Lake PCH contains two GSPI controllers. Using the common GSPI
controller driver implementation for Intel PCH, add support for GSPI
controller buses on Sky Lake/Kaby Lake.

BUG=b:35583330

Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2017-04-06 00:45:36 +02:00

..

broadcom/cygnus

vboot: Move remaining features out of vendorcode/google/chromeos

2017-03-28 22:18:13 +02:00

dmp/vortex86ex

src/soc: Capitalize CPU, ACPI, RAM and ROM

2016-07-31 19:27:53 +02:00

imgtec/pistachio

spi: Get rid of SPI_ATOMIC_SEQUENCING

2016-12-23 04:54:55 +01:00

intel

soc/intel/skylake: Add support for GSPI controller

2017-04-06 00:45:36 +02:00

lowrisc/lowrisc

soc/lowrisc: Place CBMEM at top of autodetected RAM

2016-12-06 18:51:13 +01:00

marvell

vboot: Move remaining features out of vendorcode/google/chromeos

2017-03-28 22:18:13 +02:00

mediatek/mt8173

vboot: Move remaining features out of vendorcode/google/chromeos

2017-03-28 22:18:13 +02:00

nvidia

vboot: Move remaining features out of vendorcode/google/chromeos

2017-03-28 22:18:13 +02:00

qualcomm

Remove libverstage as separate library and source file class

2017-03-28 22:18:53 +02:00

rdc/r8610

rdc/r8610: Move to src/soc

2016-05-05 20:08:58 +02:00

rockchip

Remove libverstage as separate library and source file class

2017-03-28 22:18:53 +02:00

samsung

vboot: Select SoC-specific configuration for all Chrome OS boards

2017-03-28 22:12:54 +02:00

ucb/riscv

soc/ucb/riscv: Place CBMEM at top of autodetected RAM

2016-12-06 18:48:28 +01:00