078bc41ce2
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
91 lines
2.7 KiB
C
91 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <superio/ite/it8718f/it8718f.h>
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#include <superio/ite/common/ite.h>
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#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
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#define EC_DEV PNP_DEV(0x2e, IT8718F_EC)
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/* Early mainboard specific GPIO setup.
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* We should use standard gpio.h eventually
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*/
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void bootblock_mainboard_early_init(void)
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{
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pci_devfn_t dev;
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/* Southbridge GPIOs. */
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dev = PCI_DEV(0x0, 0x1f, 0x0);
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/* Set default GPIOs on superio */
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ite_reg_write(GPIO_DEV, 0x25, 0x00);
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ite_reg_write(GPIO_DEV, 0x26, 0xc7);
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ite_reg_write(GPIO_DEV, 0x27, 0x80);
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ite_reg_write(GPIO_DEV, 0x28, 0x41);
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ite_reg_write(GPIO_DEV, 0x29, 0x0a);
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ite_reg_write(GPIO_DEV, 0x2c, 0x01);
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ite_reg_write(GPIO_DEV, 0x62, 0x08);
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ite_reg_write(GPIO_DEV, 0x72, 0x00);
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ite_reg_write(GPIO_DEV, 0x73, 0x00);
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ite_reg_write(GPIO_DEV, 0xb8, 0x00);
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ite_reg_write(GPIO_DEV, 0xbb, 0x40);
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ite_reg_write(GPIO_DEV, 0xc0, 0x00);
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ite_reg_write(GPIO_DEV, 0xc1, 0xc7);
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ite_reg_write(GPIO_DEV, 0xc2, 0x80);
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ite_reg_write(GPIO_DEV, 0xc3, 0x01);
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ite_reg_write(GPIO_DEV, 0xc4, 0x0a);
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ite_reg_write(GPIO_DEV, 0xc8, 0x00);
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ite_reg_write(GPIO_DEV, 0xc9, 0x04);
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ite_reg_write(GPIO_DEV, 0xcb, 0x00);
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ite_reg_write(GPIO_DEV, 0xcc, 0x02);
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ite_reg_write(GPIO_DEV, 0xf0, 0x10);
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ite_reg_write(GPIO_DEV, 0xf1, 0x40);
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ite_reg_write(GPIO_DEV, 0xf6, 0x26);
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ite_reg_write(GPIO_DEV, 0xfc, 0x52);
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ite_reg_write(EC_DEV, 0xf0, 0x80);
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ite_reg_write(EC_DEV, 0xf1, 0x00);
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ite_reg_write(EC_DEV, 0xf2, 0x0a);
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ite_reg_write(EC_DEV, 0xf3, 0x80);
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ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
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ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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/* Disable SIO reboot */
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ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
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/* IRQ routing */
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RCBA32(D31IP) = 0x00002210;
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RCBA32(D30IP) = 0x00002100;
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RCBA32(D29IP) = 0x10004321;
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RCBA32(D28IP) = 0x00214321;
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RCBA32(D27IP) = 0x00000001;
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RCBA32(D31IR) = 0x00410032;
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RCBA32(D29IR) = 0x32100237;
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RCBA32(D27IR) = 0x00000000;
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}
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void mb_get_spd_map(u8 spd_map[4])
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{
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spd_map[0] = 0x50;
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spd_map[2] = 0x52;
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}
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