07dd73c921
Extend support for CrashLog to Intel Jasperlake based platforms.
This commit is based on 15cbc3b599,
originally reviewed on https://review.coreboot.org/c/coreboot/+/49943.
BUG=b:354834461
TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms
and can generate a BERT table, if enabled.
Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
63 lines
1.3 KiB
Makefile
63 lines
1.3 KiB
Makefile
## SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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# all (bootblock, verstage, romstage, postcar, ramstage)
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all-y += gspi.c
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all-y += i2c.c
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all-y += pmutil.c
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all-y += spi.c
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all-y += uart.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += espi.c
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bootblock-y += gpio.c
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bootblock-y += p2sb.c
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romstage-y += espi.c
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romstage-y += gpio.c
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romstage-y += meminit.c
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romstage-y += pcie_rp.c
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romstage-y += reset.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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ramstage-y += lockdown.c
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ramstage-y += p2sb.c
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ramstage-y += pcie_rp.c
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ramstage-y += pmc.c
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ramstage-y += reset.c
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ramstage-y += systemagent.c
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ramstage-y += sd.c
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ramstage-y += xhci.c
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ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += uart.c
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smm-y += elog.c
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smm-y += xhci.c
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verstage-y += gpio.c
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CPPFLAGS_common += -I$(src)/soc/intel/jasperlake
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CPPFLAGS_common += -I$(src)/soc/intel/jasperlake/include
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9c-00
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endif
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