0867062412
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
138 lines
2.7 KiB
Plaintext
138 lines
2.7 KiB
Plaintext
/* Copyright 2000 AG Electronics Ltd. */
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/* This code is distributed without warranty under the GPL v2 (see COPYING) */
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#define ASM
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#include "ppcreg.h"
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#include <ppc_asm.tmpl>
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.section ".rom.reset", "ax", @progbits
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.globl _start
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_start:
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b system_reset
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.section ".rom.exception_vectors", "ax", @progbits
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%%EXCEPTION_VECTOR_TABLE%%
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.section ".rom.data", "a", @progbits
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.section ".rom.text", "ax", @progbits
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system_reset:
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/*
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* Do processor family initialization
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*/
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%%FAMILY_INIT%%
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/*
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* Do processor specific initialization
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*/
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%%PROCESSOR_INIT%%
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#if CONFIG_USE_DCACHE_RAM == 1
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#define DCACHE_RAM_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
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/*
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* Initialize data cache blocks
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* (assumes cache block size of 32 bytes)
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*
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* NOTE: This may need to be moved to FAMILY_INIT if
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* dcbz is not supported on all CPU's
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*/
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lis r1, CONFIG_DCACHE_RAM_BASE@h
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ori r1, r1, CONFIG_DCACHE_RAM_BASE@l
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li r3, (CONFIG_DCACHE_RAM_SIZE / 32)
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mtctr r3
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0: dcbz r0, r1
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addi r1, r1, 32
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bdnz 0b
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/*
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* Set up stack in cache. The SP must be 16-byte (4-word) aligned
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* for SYSV EABI or 8-byte (2-word) aligned for PPC EABI, so we make
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* it 16-byte aligned to cover both cases. Also we have to ensure that
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* the first word is located within the cache.
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*/
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lis r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h
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ori r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l
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lis r0, 0
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stwu r0, -4(r1)
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stwu r0, -4(r1)
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stwu r0, -4(r1)
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stwu r0, -4(r1)
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#if 0
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/*
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* Clear stack
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*/
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lis r4, CONFIG_DCACHE_RAM_BASE@h
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ori r4, r4, CONFIG_DCACHE_RAM_BASE@l
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lis r7, DCACHE_RAM_END@h
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ori r7, r7, DCACHE_RAM_END@l
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lis r5, 0
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1: stwx r5, 0, r4
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addi r4, r4, 4
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cmp 0, 0, r4, r7
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ble 1b
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sync
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#endif
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/*
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* Set up the EABI pointers, before we enter any C code
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*/
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lis r13, _SDA_BASE_@h
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ori r13, r13, _SDA_BASE_@l
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lis r2, _SDA2_BASE_@h
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ori r2, r2, _SDA2_BASE_@l
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/*
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* load start address into SRR0 for rfi
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*/
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lis r3, ppc_main@h
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ori r3, r3, ppc_main@l
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mtspr SRR0, r3
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/*
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* load the current MSR into SRR1 so that it will be copied
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* back into MSR on rfi
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*/
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mfmsr r4
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mtspr SRR1, r4 // load SRR1 with r4
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/*
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* If something returns after rfi then die
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*/
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lis r3, dead@h
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ori r3, r3, dead@l
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mtlr r3
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/*
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* Complete rest of initialization in C (ppc_main)
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*/
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rfi
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#endif /* CONFIG_USE_DCACHE_RAM */
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/*
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* Stop here if something goes wrong
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*/
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dead:
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b dead
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/*NOTREACHED*/
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/* Remove need for ecrti.o and ectrn.o */
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.globl __init
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__init:
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.globl __fini
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__fini:
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.globl __CTOR_LIST__
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__CTOR_LIST__:
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.globl __CTOR_END__
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__CTOR_END__:
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.globl __DTOR_LIST__
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__DTOR_LIST__:
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.globl __DTOR_END__
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__DTOR_END__:
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blr
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%%NORTHBRIDGE_INIT%%
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