535 lines
9.1 KiB
C
535 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#ifndef __ACPI__
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#define PAD_CFG_NC(pad) PAD_NC(pad, NONE)
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/* Early pad configuration in romstage. */
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static const struct pad_config early_gpio_table[] = {
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// UART2
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// UART2_RXD
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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// UART2_TXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NC(GPP_C22),
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// NC
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PAD_CFG_NC(GPP_C23),
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};
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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// GPD
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// Power Management
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// PM_BATLOW#
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PAD_CFG_NC(GPD0),
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// AC_PRESENT
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PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
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// NC
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PAD_CFG_NC(GPD2),
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// PWR_BTN#
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PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
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// SUSB#_PCH
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PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
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// SUSC#_PCH
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PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
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// SLP_A#
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PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
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// GPIO
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// NC
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PAD_CFG_NC(GPD7),
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// Clock Signals
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// SUS_CLK
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PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
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// Power Management
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// GPD9_RTD3
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PAD_CFG_NC(GPD9),
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// NC
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PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NC(GPD11),
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// GPP_A
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// LPC
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// SB_KBCRST#
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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// LPC_AD0
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
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// LPC_AD1
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
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// LPC_AD2
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
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// LPC_AD3
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
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// LPC_FRAME#
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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// SERIRQ with pull up
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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// GSPI0
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// TPM_PIRQ#
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PAD_CFG_NC(GPP_A7),
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// LPC
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// PM_CLKRUN# with pull-up
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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// PCLK_KBC
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
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// NC
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PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
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// GSPI1
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// NC
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PAD_CFG_NC(GPP_A11),
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// ISH_GP
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// PCH_GPP_A12
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PAD_CFG_NC(GPP_A12),
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// Power Management
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// SUSWARN#
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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// LPC
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// NC
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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// Power Management
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// SUS_PWR_ACK
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PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
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// SD
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// NC
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PAD_CFG_NC(GPP_A16),
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// LIGHT_KB_DET#
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PAD_CFG_NC(GPP_A17),
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// ISH_GP
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// NC
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PAD_CFG_NC(GPP_A18),
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// SATA_PWR_EN
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PAD_CFG_GPO(GPP_A19, 1, DEEP),
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// NC
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PAD_CFG_NC(GPP_A20),
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// NC
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PAD_CFG_NC(GPP_A21),
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// PS8338B_SW
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PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
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// PS8338B_PCH
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PAD_CFG_NC(GPP_A23),
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// GPP_B
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// Power
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// CORE_VID0
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PAD_CFG_NC(GPP_B0),
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// CORE_VID1
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PAD_CFG_NC(GPP_B1),
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// Power Management
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// CNVI_WAKE#
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PAD_CFG_NC(GPP_B2),
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// CPU Misc
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// NC
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PAD_CFG_NC(GPP_B3),
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// NC
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PAD_CFG_NC(GPP_B4),
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// Clock Signals
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// NC
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PAD_CFG_NC(GPP_B5),
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// NC
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PAD_CFG_NC(GPP_B6),
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// WLAN_CLKREQ#
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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// LAN_CLKREQ#
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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// TBT_CLKREQ#
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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// SSD_CLKREQ#
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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// Power Management
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// EXT_PWR_GATE#
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PAD_CFG_NC(GPP_B11),
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// SLP_S0#
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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// PLT_RST#
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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// SPKR
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// PCH_SPKR
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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// GSPI0
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// NC
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PAD_CFG_NC(GPP_B15),
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// PCH_GPP_B16
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PAD_CFG_NC(GPP_B16),
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// PCH_GPP_B17
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PAD_CFG_NC(GPP_B17),
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// PCH_GPP_B18 - strap for disabling no reboot mode
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PAD_CFG_NC(GPP_B18),
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// GSPI1
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// NC
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PAD_CFG_NC(GPP_B19),
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// NC
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PAD_CFG_NC(GPP_B20),
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// NC
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PAD_CFG_NC(GPP_B21),
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// PCH_GPP_B22
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PAD_CFG_NC(GPP_B22),
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// SMBUS
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// NC
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PAD_CFG_NC(GPP_B23),
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// GPP_C
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// SMBUS
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// SMB_CLK_DDR
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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// SMB_DAT_DDR
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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// PCH_GPP_C2 with pull-up
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PAD_CFG_NC(GPP_C2),
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// NC
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PAD_CFG_NC(GPP_C3),
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// NC
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PAD_CFG_NC(GPP_C4),
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// NC
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PAD_CFG_NC(GPP_C5),
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// LAN_WAKEUP#
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PAD_CFG_NC(GPP_C6),
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// NC
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PAD_CFG_NC(GPP_C7),
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// UART0
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// NC
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PAD_CFG_NC(GPP_C8),
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// TBCIO_PLUG_EVENT
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_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000),
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// TBT_FRC_PWR
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PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
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// NC
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PAD_CFG_NC(GPP_C11),
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// UART1
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// GPP_C12_RTD3
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PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
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// SSD_PWR_DN#
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PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
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// TBTA_HRESET
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PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
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// TBT_PERST_N
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PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST),
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// I2C
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// T_SDA
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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// T_SCL
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NC(GPP_C18),
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// SWI
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PAD_CFG_NC(GPP_C19),
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// UART2
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// UART2_RXD
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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// UART2_TXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NC(GPP_C22),
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// NC
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PAD_CFG_NC(GPP_C23),
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// GPP_D
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// SPI1
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// NC
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PAD_CFG_NC(GPP_D0),
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// NC
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PAD_CFG_NC(GPP_D1),
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// NC
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PAD_CFG_NC(GPP_D2),
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// NC
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PAD_CFG_NC(GPP_D3),
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// IMGCLKOUT
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// NC
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PAD_CFG_NC(GPP_D4),
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// I2C
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// NC
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PAD_CFG_NC(GPP_D5),
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// NC
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PAD_CFG_NC(GPP_D6),
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// NC
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PAD_CFG_NC(GPP_D7),
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// SB_BLON
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PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
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// GSPI2
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// SWI#
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_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
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// NC
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PAD_CFG_NC(GPP_D10),
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// RTD3_PCIE_WAKE#
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_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
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// PCH_GPP_D12
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PAD_CFG_NC(GPP_D12),
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// UART0
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// NC
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PAD_CFG_NC(GPP_D13),
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// NC
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PAD_CFG_NC(GPP_D14),
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// NC
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PAD_CFG_NC(GPP_D15),
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// RTD3_3G_PW R_EN
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PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
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// DMIC
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// NC
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PAD_CFG_NC(GPP_D17),
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// NC
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PAD_CFG_NC(GPP_D18),
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// GPPC_DMIC_CLK
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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// GPPC_DMIC_DATA
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PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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// SPI1
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// TPM_DET#
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PAD_CFG_NC(GPP_D21),
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// TPM_TCM_Detect
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PAD_CFG_NC(GPP_D22),
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// I2S
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// NC
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PAD_CFG_NC(GPP_D23),
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// GPP_E
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// SATA
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// PCH_GPP_E0 with pull-up
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PAD_CFG_NC(GPP_E0),
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// SATA_ODD_PRSNT#
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PAD_CFG_NC(GPP_E1),
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// SATAGP2
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PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
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// CPU Misc
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// NC
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PAD_CFG_NC(GPP_E3),
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// DEVSLP
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// NC
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PAD_CFG_NC(GPP_E4),
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// NC
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PAD_CFG_NC(GPP_E5),
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// DEVSLP2
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PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
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// CPU Misc
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// NC
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PAD_CFG_NC(GPP_E7),
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// SATA
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// PCH_SATAHDD_LED#
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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// USB2
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// GP_BSSB_CLK
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PAD_CFG_NC(GPP_E9),
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// GPP_E10
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PAD_CFG_NC(GPP_E10),
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// GPP_E11
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PAD_CFG_NC(GPP_E11),
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// USB_OC#78
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PAD_CFG_NC(GPP_E12),
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// Display Signals
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// MUX_HPD
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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// HDMI_HPD
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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// SMI#
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_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0),
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// SCI#
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_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
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// EDP_HPD
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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// MDP_CTRLCLK
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PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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// MDP_CTRLDATA
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PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
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// HDMI_CTRLCLK
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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// HDMI_CTRLDATA
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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// NC
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PAD_CFG_NC(GPP_E22),
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// NC
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PAD_CFG_NC(GPP_E23),
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// GPP_F
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// CNVI
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// CNVI_GNSS_PA_BLANKING
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
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// GPIO
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// NC
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PAD_CFG_NC(GPP_F1),
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// NC
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PAD_CFG_NC(GPP_F2),
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// NC
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PAD_CFG_NC(GPP_F3),
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// CNVI
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// CNVI_BRI_DT
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
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// CNVI_BRI_RSP
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PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
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// CNVI_RGI_DT
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
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// CNVI_RGI_RSP
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PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
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// CNVI_MFUART2_RXD
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PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
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// CNVI_MFUART2_TXD
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PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
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// GPIO
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// NC
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PAD_CFG_NC(GPP_F10),
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// EMMC
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// NC
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PAD_CFG_NC(GPP_F11),
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// NC
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PAD_CFG_NC(GPP_F12),
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// NC
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PAD_CFG_NC(GPP_F13),
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// NC
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PAD_CFG_NC(GPP_F14),
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// NC
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PAD_CFG_NC(GPP_F15),
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// NC
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PAD_CFG_NC(GPP_F16),
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// NC
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PAD_CFG_NC(GPP_F17),
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// NC
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PAD_CFG_NC(GPP_F18),
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// NC
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PAD_CFG_NC(GPP_F19),
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// NC
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PAD_CFG_NC(GPP_F20),
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// NC
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PAD_CFG_NC(GPP_F21),
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// NC
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PAD_CFG_NC(GPP_F22),
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// A4WP
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// A4WP_PRESENT
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PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
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// GPP_G
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// SD
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// EDP_DET
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PAD_CFG_NC(GPP_G0),
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// NC
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PAD_CFG_NC(GPP_G1),
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// NC
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PAD_CFG_NC(GPP_G2),
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// ASM1543_I_SEL0
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PAD_CFG_NC(GPP_G3),
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// ASM1543_I_SEL1
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PAD_CFG_NC(GPP_G4),
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// BOARD_ID
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PAD_CFG_NC(GPP_G5),
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// NC
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PAD_CFG_NC(GPP_G6),
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// TBT_Detect
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PAD_CFG_NC(GPP_G7),
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// GPP_H
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// CNVI
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// NC
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PAD_CFG_NC(GPP_H0),
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// CNVI_RST#
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PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
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// CNVI_CLKREQ
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PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
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// NC
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PAD_CFG_NC(GPP_H3),
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// I2C
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// T23
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PAD_CFG_NC(GPP_H4),
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// T22
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PAD_CFG_NC(GPP_H5),
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// NC
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PAD_CFG_NC(GPP_H6),
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// NC
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PAD_CFG_NC(GPP_H7),
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// NC
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PAD_CFG_NC(GPP_H8),
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// NC
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PAD_CFG_NC(GPP_H9),
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// I2C
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// NC
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PAD_CFG_NC(GPP_H10),
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// NC
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PAD_CFG_NC(GPP_H11),
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// PCIE
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// NC
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PAD_CFG_NC(GPP_H12),
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// NC
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PAD_CFG_NC(GPP_H13),
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// G_INT1
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PAD_CFG_NC(GPP_H14),
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// NC
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PAD_CFG_NC(GPP_H15),
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// Display Signals
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// NC
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PAD_CFG_NC(GPP_H16),
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// NC
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PAD_CFG_NC(GPP_H17),
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// CPU Power
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// CPU_C10_GATE#
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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// TIMESYNC
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// NC
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PAD_CFG_NC(GPP_H19),
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// IMGCLKOUT
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// NC
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PAD_CFG_NC(GPP_H20),
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// GPIO
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// GPPC_H21
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PAD_CFG_NC(GPP_H21),
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// TBT_RTD3_PWR_EN_R
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PAD_NC(GPP_H22, NONE),
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// NC, WIGIG_PEWAKE
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PAD_CFG_NC(GPP_H23),
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};
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#endif
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#endif
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