0a4457ff44
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
54 lines
1.2 KiB
Plaintext
54 lines
1.2 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config NORTHBRIDGE_INTEL_X4X
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bool
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if NORTHBRIDGE_INTEL_X4X
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config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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def_bool y
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select HAVE_DEBUG_RAM_SETUP
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select LAPIC_MONOTONIC_TIMER
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select VGA
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select INTEL_GMA_ACPI
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select CACHE_MRC_SETTINGS
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select PARALLEL_MP
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config CBFS_SIZE
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hex
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default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/x4x/bootblock.c"
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config VGA_BIOS_ID
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string
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default "8086,2e32"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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endif
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