0aa37c488b
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
110 lines
3.5 KiB
Plaintext
110 lines
3.5 KiB
Plaintext
# sample config for amd/bimini_fam10
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chip northbridge/amd/amdfam10/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/socket_ASB2 #L1 and DDR3
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device lapic 0 on end
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end
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end
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device domain 0 on
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subsystemid 0x1022 0x3060 inherit
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chip northbridge/amd/amdfam10
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device pci 18.0 on # northbridge
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chip southbridge/amd/rs780
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device pci 0.0 on end # HT 0x9600
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
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device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
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device pci 3.0 off end # PCIE P2P bridge 0x960b
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device pci 4.0 on end # PCIE P2P bridge 0x9604
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device pci 5.0 on end # PCIE P2P bridge 0x9605
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device pci 6.0 on end # PCIE P2P bridge 0x9606
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device pci 7.0 on end # PCIE P2P bridge 0x9607
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device pci 8.0 off end # NB/SB Link P2P bridge
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device pci 9.0 on end #
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device pci a.0 off end #
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register "gppsb_configuration" = "4" # Configuration E
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register "gpp_configuration" = "2" # Configuration C
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register "port_enable" = "0x6fc"
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register "gfx_dev2_dev3" = "1"
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register "gfx_dual_slot" = "0"
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register "gfx_lane_reversal" = "0"
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register "gfx_tmds" = "0"
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register "gfx_compliance" = "0"
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register "gfx_reconfiguration" = "1"
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register "gfx_link_width" = "0"
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end
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chip southbridge/amd/sb800 # it is under NB/SB Link, but on the same pci bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.2 on end # USB
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device pci 13.0 on end # USB
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device pci 13.2 on end # USB
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device pci 14.0 on # SM
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
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end # SM
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device pci 14.1 on end # IDE 0x439c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on end # LPC 0x439d
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device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO.
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device pci 14.5 on end # USB 2
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device pci 14.6 on end # Gec
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device pci 15.0 on end # PCIe 0
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device pci 15.1 on end # PCIe 1
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device pci 15.2 on end # PCIe 2
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device pci 15.3 on end # PCIe 3
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device pci 16.0 on end # USB
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device pci 16.2 on end # USB
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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register "gpp_configuration" = "4"
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end #southbridge/amd/sb800
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end # device pci 18.0
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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end
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end #domain
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#for node 32 to node 63
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# device domain 0 on
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# chip northbridge/amd/amdfam10
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# device pci 00.0 on end# northbridge
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# device pci 00.0 on end
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# device pci 00.0 on end
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# device pci 00.0 on end
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# device pci 00.1 on end
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# device pci 00.2 on end
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# device pci 00.3 on end
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# device pci 00.4 on end
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# device pci 00.5 on end
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# end
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# end #domain
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 on end # pci_regs_all
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# device pnp 0.2 off end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 off end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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# device pnp 0.8 off end # hard reset
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# device pnp 0.9 off end # mcp55
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# device pnp 0.a on end # GH ext table
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# end
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end
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