0b0113f243
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <soc/mmu.h>
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#include <soc/mmu_common.h>
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#include <soc/symbols_common.h>
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#include <soc/cpucp.h>
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#include <soc/pcie.h>
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static struct device_operations pci_domain_ops = {
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.read_resources = &qcom_pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_host_bridge_scan_bus,
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.enable = &qcom_setup_pcie_host,
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};
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static void soc_read_resources(struct device *dev)
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{
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void *start = NULL;
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void *end = NULL;
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ram_range(dev, 0, (uintptr_t)ddr_region->offset, ddr_region->size);
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reserved_ram_range(dev, 1, (uintptr_t)_dram_soc, REGION_SIZE(dram_soc));
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reserved_ram_range(dev, 2, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan));
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reserved_ram_range(dev, 3, (uintptr_t)_dram_wpss, REGION_SIZE(dram_wpss));
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reserved_ram_range(dev, 4, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
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reserved_ram_range(dev, 5, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp));
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if (soc_modem_carve_out(&start, &end))
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reserved_ram_range(dev, 6, (uintptr_t)start, end - start);
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}
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static void soc_init(struct device *dev)
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{
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cpucp_fw_load_reset();
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}
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static struct device_operations soc_ops = {
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.read_resources = soc_read_resources,
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.set_resources = noop_set_resources,
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.init = soc_init,
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};
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static void enable_soc_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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if (mainboard_needs_pcie_init())
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dev->ops = &pci_domain_ops;
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else
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printk(BIOS_DEBUG, "Skip setting PCIe ops\n");
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &soc_ops;
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}
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struct chip_operations soc_qualcomm_sc7280_ops = {
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CHIP_NAME("SOC Qualcomm SC7280")
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.enable_dev = enable_soc_dev,
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};
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