0b101fc338
Hook up microcode from 3rdparty repo for: - 06-b7-01 (CPUID signature: 0xb0671) Verified microcode blob was in CBFS on Clevo PD50SNE (system76/serw13), which has an i9-13900HX. Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
115 lines
3.2 KiB
Makefile
115 lines
3.2 KiB
Makefile
## SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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# all (bootblock, verstage, romstage, postcar, ramstage)
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all-y += gspi.c
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all-y += i2c.c
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all-y += pmutil.c
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all-y += spi.c
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all-y += uart.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += espi.c
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bootblock-y += p2sb.c
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bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c
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romstage-y += espi.c
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romstage-y += meminit.c
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romstage-y += pcie_rp.c
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romstage-y += reset.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += graphics.c
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ramstage-y += hsphy.c
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ramstage-y += lockdown.c
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ramstage-y += p2sb.c
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ramstage-y += pcie_rp.c
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ramstage-y += pmc.c
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ramstage-y += reset.c
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ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
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ramstage-y += soundwire.c
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ramstage-y += systemagent.c
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ramstage-y += tcss.c
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ramstage-y += vr_config.c
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ramstage-y += xhci.c
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ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
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smm-y += elog.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += uart.c
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smm-y += xhci.c
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ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
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bootblock-y += gpio_pch_s.c
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romstage-y += gpio_pch_s.c
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ramstage-y += gpio_pch_s.c
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smm-y += gpio_pch_s.c
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verstage-y += gpio_pch_s.c
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else
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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smm-y += gpio.c
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verstage-y += gpio.c
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endif
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CPPFLAGS_common += -I$(src)/soc/intel/alderlake
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CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
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ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
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# 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples
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# 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples
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# ADL-S/HX C0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-02
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# ADL-S H0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05
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# RPL-S/HX B0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01
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else
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ifneq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
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# 06-9a-00, 06-9a-01 are ADL-P/ADL-M Engineering Samples
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# Missing 06-9a-02 ADL-P K0
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# ADL-P L0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-03
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# ADL-P R0 and ADL-M R0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-04
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endif
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endif
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ifeq ($(CONFIG_STITCH_ME_BIN),y)
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$(eval $(call cse_add_dummy_to_bp1_bp2,DLMP))
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$(eval $(call cse_add_dummy_to_bp1_bp2,IFPP))
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$(eval $(call cse_add_dummy_to_bp1_bp2,SBDT))
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$(eval $(call cse_add_decomp_to_bp1_bp2,RBEP))
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$(eval $(call cse_add_dummy_to_bp1_bp2,UFSP))
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$(eval $(call cse_add_dummy_to_bp1_bp2,UFSG))
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$(eval $(call cse_add_input_to_bp1_bp2,OEMP))
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$(eval $(call cse_add_input_to_bp1_bp2,PMCP))
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$(eval $(call cse_add_decomp,bp1,MFTP))
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$(eval $(call cse_add_decomp,bp2,FTPR))
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$(eval $(call cse_add_input_to_bp1_bp2,IOMP))
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$(eval $(call cse_add_input_to_bp1_bp2,NPHY))
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$(eval $(call cse_add_input_to_bp1_bp2,TBTP))
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$(eval $(call cse_add_input_to_bp1_bp2,PCHC))
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$(eval $(call cse_add_decomp,bp2,NFTP))
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$(eval $(call cse_add_dummy,bp2,ISHP))
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$(eval $(call cse_add_input,bp2,IUNP))
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endif
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endif
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