0b1a5a4a92
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
48 lines
1.0 KiB
C
48 lines
1.0 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "pc80/mc146818rtc_early.c"
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#include "southbridge/intel/i82801ca/cmos_failover.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/intel/e7501/reset_test.c"
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static unsigned long main(unsigned long bist)
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{
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/* Is this a deliberate reset by the bios */
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if (bios_reset_detected() && last_boot_normal()) {
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goto normal_image;
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}
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/* This is the primary cpu how should I boot? */
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else {
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check_cmos_failed();
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if (do_normal_boot()) {
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goto normal_image;
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}
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else {
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goto fallback_image;
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}
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}
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normal_image:
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asm volatile ("jmp __normal_image"
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: /* outputs */
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: "a" (bist) /* inputs */
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: /* clobbers */
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);
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#if 0
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cpu_reset:
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asm volatile ("jmp __cpu_reset"
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: /* outputs */
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: "a"(bist) /* inputs */
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: /* clobbers */
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);
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#endif
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fallback_image:
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return bist;
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}
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