0b7813fe97
Change-Id: Ia46b622c52f98d4cc5fb7d9b02e2aeb366ef3915 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pnp.h>
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#include <superio/conf_mode.h>
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#include <superio/hwm5_conf.h>
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#include <console/console.h>
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#include <pc80/keyboard.h>
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#include <option.h>
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#include "w83627ehg.h"
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static void enable_hwm_smbus(struct device *dev)
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{
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u8 reg8;
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/* Configure pins 89/90 as SDA/SCL (I2C bus). */
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reg8 = pnp_read_config(dev, 0x2a);
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reg8 |= (1 << 1);
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pnp_write_config(dev, 0x2a, reg8);
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}
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static void init_acpi(struct device *dev)
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{
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u8 value;
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int power_on = get_int_option("power_on_after_fail", 1);
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pnp_enter_conf_mode(dev);
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pnp_set_logical_device(dev);
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value = pnp_read_config(dev, 0xe4);
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value &= ~(3 << 5);
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if (power_on)
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value |= (1 << 5);
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pnp_write_config(dev, 0xe4, value);
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pnp_exit_conf_mode(dev);
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}
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static void init_hwm(u16 base)
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{
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int i;
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u8 reg, value;
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/* reg mask data */
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u8 hwm_reg_values[] = {
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0x40, 0xff, 0x81, /* Start HWM. */
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0x48, 0x7f, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
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};
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for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
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reg = hwm_reg_values[i];
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value = pnp_read_hwm5_index(base, reg);
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value &= 0xff & (~(hwm_reg_values[i + 1]));
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value |= 0xff & hwm_reg_values[i + 2];
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printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
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"value = 0x%02x\n", base, reg, value);
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pnp_write_hwm5_index(base, reg, value);
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}
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}
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static void w83627ehg_init(struct device *dev)
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{
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struct resource *res0;
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if (!dev->enabled)
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return;
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switch (dev->path.pnp.device) {
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case W83627EHG_KBC:
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pc_keyboard_init(NO_AUX_DEVICE);
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break;
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case W83627EHG_HWM:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_hwm(res0->base);
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break;
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case W83627EHG_ACPI:
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init_acpi(dev);
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break;
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}
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}
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static void w83627ehg_pnp_enable_resources(struct device *dev)
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{
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pnp_enable_resources(dev);
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pnp_enter_conf_mode(dev);
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switch (dev->path.pnp.device) {
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case W83627EHG_HWM:
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printk(BIOS_DEBUG, "W83627EHG HWM SMBus enabled\n");
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enable_hwm_smbus(dev);
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break;
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}
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pnp_exit_conf_mode(dev);
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = w83627ehg_pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = w83627ehg_init,
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.ops_pnp_mode = &pnp_conf_mode_8787_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ NULL, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
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{ NULL, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
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{ NULL, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
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{ NULL, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
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{ NULL, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
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0x07ff, 0x07ff, },
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{ NULL, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, 0x07f8, },
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{ NULL, W83627EHG_WDTO_PLED, },
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{ NULL, W83627EHG_ACPI, PNP_IRQ0, },
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{ NULL, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },
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{ NULL, W83627EHG_GAME, PNP_IO0, 0x07ff, },
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{ NULL, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, 0, 0x07fe, },
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{ NULL, W83627EHG_GPIO1, },
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{ NULL, W83627EHG_GPIO2, },
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{ NULL, W83627EHG_GPIO3, },
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{ NULL, W83627EHG_GPIO4, },
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{ NULL, W83627EHG_GPIO5, },
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{ NULL, W83627EHG_GPIO6, },
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_winbond_w83627ehg_ops = {
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CHIP_NAME("Winbond W83627EHG Super I/O")
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.enable_dev = enable_dev,
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};
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