e98d72e2a3
Remove the unused Kconfig values which specify the PDAT file, its location and inclusion into the coreboot file system. Remove the code in romstage which locates the pdat.bin file. TEST=Build and run on Galileo Gen2 Change-Id: I397aa22ada6c073c60485a735d6e2cb42bfd40ab Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15205 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
66 lines
1.9 KiB
Makefile
66 lines
1.9 KiB
Makefile
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015-2016 Intel Corporation.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-y += bootblock/esram_init.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += i2c.c
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bootblock-y += reg_access.c
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bootblock-y += tsc_freq.c
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bootblock-y += uart_common.c
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romstage-y += i2c.c
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romstage-y += memmap.c
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romstage-y += reg_access.c
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romstage-y += tsc_freq.c
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romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += ehci.c
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ramstage-y += gpio_i2c.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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ramstage-y += memmap.c
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ramstage-y += northcluster.c
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ramstage-y += reg_access.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/quark
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CPPFLAGS_common += -I$(src)/soc/intel/quark/include
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# Chipset microcode path
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CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
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# Add the FSP binary to the CBFS image
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cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
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fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
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fsp.bin-position := $(CONFIG_FSP_LOC)
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fsp.bin-type := raw
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# Add the chipset microcode file to the CBFS image
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cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
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rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
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rmu.bin-position := $(CONFIG_RMU_LOC)
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rmu.bin-type := raw
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endif # CONFIG_SOC_INTEL_QUARK
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