0cca6e24b7
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
43 lines
1.1 KiB
Plaintext
43 lines
1.1 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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/* global NVS and variables */
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#include <soc/intel/apollolake/acpi/globalnvs.asl>
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/* CPU */
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#include <soc/intel/apollolake/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/apollolake/acpi/northbridge.asl>
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#include <soc/intel/apollolake/acpi/southbridge.asl>
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#include <soc/intel/apollolake/acpi/pch_hda.asl>
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}
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}
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/* Chipset specific sleep states */
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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}
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