Arthur Heymans 0d1c9b0e32 nb/intel/x4x: Add DDR3 rcomp ...

Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19875
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2018-05-14 07:42:38 +00:00

..

acpi

nb/intel/x4x: Correct typos in interrupt routing for PEG

2016-09-07 19:06:42 +02:00

acpi.c

nb/x4x: Get rid of device_t

2018-04-30 09:22:32 +00:00

bootblock.c

nb/intel/x4x: Fix issues found by checkpatch.pl

2017-03-21 20:11:15 +01:00

chip.h

northbridge/intel/x4x: Intel 4-series northbridge support

2015-12-29 18:03:33 +01:00

dq_dqs.c

nb/intel/x4x: Implement both read and write training

2018-05-01 17:41:31 +00:00

early_init.c

nb/intel/x4x: Change memory layout to improve MTRR

2018-05-01 17:42:30 +00:00

gma.c

nb/x4x: Get rid of device_t

2018-04-30 09:22:32 +00:00

iomap.h

nb/intel/x4x: Fix issues found by checkpatch.pl

2017-03-21 20:11:15 +01:00

Kconfig

nb/intel/x4x: Use SPI flash to cache raminit results

2018-04-17 10:39:45 +00:00

Makefile.inc

nb/intel/x4x: Rename a things that are not specific to DDR2

2018-05-14 07:40:49 +00:00

northbridge.c

{mb,nb,soc}: Remove references to pci_bus_default_ops()

2018-05-08 03:01:04 +00:00

ram_calc.c

nb/intel/x4x: Fix issues found by checkpatch.pl

2017-03-21 20:11:15 +01:00

raminit_ddr23.c

nb/intel/x4x: Add DDR3 rcomp

2018-05-14 07:42:38 +00:00

raminit_tables.c

nb/intel/x4x: Add a convenient macro to loop over bytelanes

2018-04-17 10:41:14 +00:00

raminit.c

nb/intel/x4x: Rename a things that are not specific to DDR2

2018-05-14 07:40:49 +00:00

rcven.c

nb/intel/x4x/rcven.c: Change the verbosity of some messages

2018-04-17 10:41:57 +00:00

x4x.h

nb/intel/x4x/raminit: Make programming launch ddr3 specific

2018-05-14 07:41:29 +00:00