0d6ddf8da7
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
16 lines
392 B
Plaintext
16 lines
392 B
Plaintext
config CPU_INTEL_MODEL_1067X
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bool
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select SMP
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select SSE2
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_INTEL_COMMON
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select CPU_INTEL_COMMON_TIMEBASE
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select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK
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