0d8bb7427b
Add the I2C devices to skylake with the scan_bus handler for SMBUS devices so that I2C-based devices can be declared in devicetree.cb and get initialized properly during ramstage. This does not yet provide the I2C driver, but it allows for devices that are declared in devicetree.cb to provide ACPI tables to the OS. Change-Id: I9dfe4a06a8b0bc549a2b0e2d7c033c895188ba30 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14992 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
89 lines
2.2 KiB
Makefile
89 lines
2.2 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
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subdirs-y += nhlt
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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verstage-y += gpio.c
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verstage-y += memmap.c
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verstage-y += monotonic_timer.c
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verstage-y += pch.c
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verstage-y += pmutil.c
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verstage-y += pcr.c
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verstage-y += tsc_freq.c
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verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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romstage-y += flash_controller.c
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romstage-y += gpio.c
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romstage-y += memmap.c
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romstage-y += monotonic_timer.c
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romstage-y += pch.c
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romstage-y += pcr.c
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romstage-y += pei_data.c
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romstage-y += pmutil.c
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romstage-y += smbus_common.c
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romstage-y += tsc_freq.c
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romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += cpu_info.c
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ramstage-y += elog.c
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ramstage-y += finalize.c
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ramstage-y += flash_controller.c
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ramstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += fsp_reset.c
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ramstage-y += gpio.c
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ramstage-y += i2c.c
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ramstage-y += igd.c
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ramstage-y += lpc.c
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ramstage-y += me_status.c
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ramstage-y += memmap.c
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ramstage-y += monotonic_timer.c
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ramstage-y += pch.c
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ramstage-y += pcie.c
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ramstage-y += pcr.c
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ramstage-y += pei_data.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-y += ramstage.c
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ramstage-y += smbus.c
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ramstage-y += smbus_common.c
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ramstage-y += smi.c
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ramstage-y += smmrelocate.c
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ramstage-y += systemagent.c
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ramstage-y += tsc_freq.c
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ramstage-y += uart.c
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ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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ramstage-y += vr_config.c
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ramstage-y += xhci.c
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smm-y += cpu_info.c
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smm-y += gpio.c
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smm-y += monotonic_timer.c
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smm-y += pcr.c
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smm-y += pch.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_UART_DEBUG) += uart_debug.c
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# cpu_microcode_bins += ???
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CPPFLAGS_common += -I$(src)/soc/intel/skylake
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
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# Currently used for microcode path.
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CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
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ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
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endif
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