0e1e8065e3
Signed-off-by: Anders Jenbo <anders@jenbo.dk> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
984 lines
28 KiB
C
984 lines
28 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Keith Hui <buurin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <spd.h>
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#include <delay.h>
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#include <stdlib.h>
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#include "i440bx.h"
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#include "raminit.h"
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/*-----------------------------------------------------------------------------
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Macros and definitions.
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-----------------------------------------------------------------------------*/
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/* Debugging macros. */
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#if CONFIG_DEBUG_RAM_SETUP
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#define PRINT_DEBUG(x) print_debug(x)
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#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
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#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
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#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
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// no dump_pci_device in src/northbridge/intel/i440bx
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// #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
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#define DUMPNORTH()
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#else
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#define PRINT_DEBUG(x)
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#define PRINT_DEBUG_HEX8(x)
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#define PRINT_DEBUG_HEX16(x)
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#define PRINT_DEBUG_HEX32(x)
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#define DUMPNORTH()
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#endif
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#define NB PCI_DEV(0, 0, 0)
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/* SDRAMC[7:5] - SDRAM Mode Select (SMS). */
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#define RAM_COMMAND_NORMAL 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x4
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/* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as
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* defined in DRAMC[2:0].
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*
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* [0] == Normal 15.625 us -> 15.6 us
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* [1] == Reduced(.25X) 3.9 us -> 7.8 ns
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* [2] == Reduced(.5X) 7.8 us -> 7.8 us
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* [3] == Extended(2x) 31.3 us -> 31.2 us
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* [4] == Extended(4x) 62.5 us -> 62.4 us
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* [5] == Extended(8x) 125 us -> 124.8 us
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*/
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static const uint32_t refresh_rate_map[] = {
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1, 5, 5, 2, 3, 4
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};
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/* Table format: register, bitmask, value. */
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static const long register_values[] = {
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/* NBXCFG - NBX Configuration Register
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* 0x50 - 0x53
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*
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* [31:24] SDRAM Row Without ECC
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* 0 = ECC components are populated in this row
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* 1 = ECC components are not populated in this row
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* [23:19] Reserved
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* [18:18] Host Bus Fast Data Ready Enable (HBFDRE)
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* Assertion of DRAM data on host bus occurs...
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* 0 = ...one clock after sampling snoop results (default)
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* 1 = ...on the same clock the snoop result is being sampled
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* (this mode is faster by one clock cycle)
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* [17:17] ECC - EDO static Drive mode
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* 0 = Normal mode (default)
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* 1 = ECC signals are always driven
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* [16:16] IDSEL_REDIRECT
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* 0 = IDSEL1 is allocated to this bridge (default)
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* 1 = IDSEL7 is allocated to this bridge
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* [15:15] WSC# Handshake Disable
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* 1 = Uni-processor mode
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* 0 = Dual-processor mode with external IOAPIC (default)
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* [14:14] Intel Reserved
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* [13:12] Host/DRAM Frequency
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* 00 = 100 MHz
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* 01 = Reserved
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* 10 = 66 MHz
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* 11 = Reserved
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* [11:11] AGP to PCI Access Enable
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* 1 = Enable
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* 0 = Disable
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* [10:10] PCI Agent to Aperture Access Disable
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* 1 = Disable
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* 0 = Enable (default)
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* [09:09] Aperture Access Global Enable
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* 1 = Enable
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* 0 = Disable
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* [08:07] DRAM Data Integrity Mode (DDIM)
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* 00 = Non-ECC
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* 01 = EC-only
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* 10 = ECC Mode
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* 11 = ECC Mode with hardware scrubbing enabled
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* [06:06] ECC Diagnostic Mode Enable (EDME)
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* 1 = Enable
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* 0 = Normal operation mode (default)
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* [05:05] MDA Present (MDAP)
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* Works in conjunction with the VGA_EN bit.
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* VGA_EN MDAP
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* 0 x All VGA cycles are sent to PCI
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* 1 0 All VGA cycles are sent to AGP
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* 1 1 All VGA cycles are sent to AGP, except for
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* cycles in the MDA range.
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* [04:04] Reserved
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* [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO)
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* 1 = Enable
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* 0 = Disable
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* [02:02] In-Order Queue Depth (IOQD)
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* 1 = In-order queue = maximum
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* 0 = A7# is sampled asserted (i.e., 0)
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* [01:00] Reserved
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*/
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// TODO
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NBXCFG + 0, 0x00, 0x0c,
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// NBXCFG + 1, 0x00, 0xa0,
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NBXCFG + 1, 0x00, 0x80,
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NBXCFG + 2, 0x00, 0x00,
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NBXCFG + 3, 0x00, 0xff,
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/* DRAMC - DRAM Control Register
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* 0x57
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*
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* [7:6] Reserved
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* [5:5] Module Mode Configuration (MMCONFIG)
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* TODO
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* [4:3] DRAM Type (DT)
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* 00 = EDO
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* 01 = SDRAM
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* 10 = Registered SDRAM
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* 11 = Reserved
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* Note: EDO, SDRAM and Registered SDRAM cannot be mixed.
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* [2:0] DRAM Refresh Rate (DRR)
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* 000 = Refresh disabled
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* 001 = 15.6 us
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* 010 = 31.2 us
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* 011 = 62.4 us
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* 100 = 124.8 us
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* 101 = 249.6 us
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* 110 = Reserved
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* 111 = Reserved
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*/
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/* Choose SDRAM (not registered), and disable refresh for now. */
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DRAMC, 0x00, 0x08,
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/*
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* PAM[6:0] - Programmable Attribute Map Registers
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* 0x59 - 0x5f
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*
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* 0x59 [3:0] Reserved
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* 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area
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* 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS
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* 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS
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* 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS
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* 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS
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* 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS
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* 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS
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* 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS
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* 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS
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* 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS entension
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* 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS entension
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* 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS entension
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* 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS entension
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*
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* Bit assignment:
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* 00 = DRAM Disabled (all access goes to memory mapped I/O space)
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* 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space)
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* 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space)
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* 11 = Read/Write (all access goes to DRAM)
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*/
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/*
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* Map all legacy regions to RAM (read/write). This is required if
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* you want to use the RAM area from 768 KB - 1 MB. If the PAM
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* registers are not set here appropriately, the RAM in that region
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* will not be accessible, thus a RAM check of it will also fail.
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*
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* TODO: This was set in sdram_set_spd_registers().
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* Test if it still works when set here.
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*/
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PAM0, 0x00, 0x30,
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PAM1, 0x00, 0x33,
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PAM2, 0x00, 0x33,
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PAM3, 0x00, 0x33,
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PAM4, 0x00, 0x33,
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PAM5, 0x00, 0x33,
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PAM6, 0x00, 0x33,
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/* DRB[0:7] - DRAM Row Boundary Registers
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* 0x60 - 0x67
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*
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* An array of 8 byte registers, which hold the ending memory address
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* assigned to each pair of DIMMs, in 8MB granularity.
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*
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* 0x60 DRB0 = Total memory in row0 (in 8 MB)
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* 0x61 DRB1 = Total memory in row0+1 (in 8 MB)
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* 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB)
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* 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB)
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* 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB)
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* 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB)
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* 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB)
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* 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB)
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*/
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/* Set the DRBs to zero for now, this will be fixed later. */
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DRB0, 0x00, 0x00,
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DRB1, 0x00, 0x00,
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DRB2, 0x00, 0x00,
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DRB3, 0x00, 0x00,
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DRB4, 0x00, 0x00,
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DRB5, 0x00, 0x00,
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DRB6, 0x00, 0x00,
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DRB7, 0x00, 0x00,
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/* FDHC - Fixed DRAM Hole Control Register
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* 0x68
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*
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* Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB.
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*
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* [7:6] Hole Enable (HEN)
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* 00 = None
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* 01 = 512 KB - 640 KB (128 KB)
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* 10 = 15 MB - 16 MB (1 MB)
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* 11 = Reserved
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* [5:0] Reserved
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*/
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/* No memory holes. */
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FDHC, 0x00, 0x00,
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/* RPS - SDRAM Row Page Size Register
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* 0x74 - 0x75
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*
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* Sets the row page size for SDRAM. For EDO memory, the page
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* size is fixed at 2 KB.
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*
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* [15:0] Page Size (PS)
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* TODO
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*/
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// TODO
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RPS + 0, 0x00, 0x00,
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RPS + 1, 0x00, 0x00,
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/* SDRAMC - SDRAM Control Register
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* 0x76 - 0x77
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*
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* [15:10] Reserved
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* [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT)
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* 00 = Illegal
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* 01 = Add a clock delay to the lead-off clock count
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* 10 = Illegal
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* 11 = Illegal
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* [07:05] SDRAM Mode Select (SMS)
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* 000 = Normal SDRAM Operation (default)
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* 001 = NOP Command Enable
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* 010 = All Banks Precharge Enable
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* 011 = Mode Register Set Enable
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* 100 = CBR Enable
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* 101 = Reserved
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* 110 = Reserved
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* 111 = Reserved
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* [04:04] SDRAMPWR
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* 0 = 3 DIMM configuration
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* 1 = 4 DIMM configuration
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* [03:03] Leadoff Command Timing (LCT)
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* 0 = 4 CS# Clock
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* 1 = 3 CS# Clock
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* [02:02] CAS# Latency (CL)
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* 0 = 3 DCLK CAS# latency
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* 1 = 2 DCLK CAS# latency
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* [01:01] SDRAM RAS# to CAS# Delay (SRCD)
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* 0 = 3 clocks between a row activate and a read or write cmd.
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* 1 = 2 clocks between a row activate and a read or write cmd.
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* [00:00] SDRAM RAS# Precharge (SRP)
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* 0 = 3 clocks of RAS# precharge
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* 1 = 2 clocks of RAS# precharge
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*/
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#if CONFIG_SDRAMPWR_4DIMM
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SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */
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#else
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SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots.*/
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#endif
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SDRAMC + 1, 0x00, 0x00,
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/* PGPOL - Paging Policy Register
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* 0x78 - 0x79
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*
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* [15:08] Banks per Row (BPR)
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* TODO
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* 0 = 2 banks
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* 1 = 4 banks
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* [07:05] Reserved
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* [04:04] Intel Reserved
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* [03:00] DRAM Idle Timer (DIT)
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* 0000 = 0 clocks
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* 0001 = 2 clocks
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* 0010 = 4 clocks
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* 0011 = 8 clocks
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* 0100 = 10 clocks
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* 0101 = 12 clocks
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* 0110 = 16 clocks
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* 0111 = 32 clocks
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* 1xxx = Infinite (pages are not closed for idle condition)
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*/
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// TODO
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PGPOL + 0, 0x00, 0x00,
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PGPOL + 1, 0x00, 0xff,
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/* PMCR - Power Management Control Register
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* 0x7a
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*
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* [07:07] Power Down SDRAM Enable (PDSE)
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* 1 = Enable
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* 0 = Disable
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* [06:06] ACPI Control Register Enable (SCRE)
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* 1 = Enable
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* 0 = Disable (default)
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* [05:05] Suspend Refresh Type (SRT)
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* 1 = Self refresh mode
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* 0 = CBR fresh mode
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* [04:04] Normal Refresh Enable (NREF_EN)
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* 1 = Enable
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* 0 = Disable
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* [03:03] Quick Start Mode (QSTART)
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* 1 = Quick start mode for the processor is enabled
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* [02:02] Gated Clock Enable (GCLKEN)
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* 1 = Enable
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* 0 = Disable
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* [01:01] AGP Disable (AGP_DIS)
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* 1 = Disable
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* 0 = Enable
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* [00:00] CPU reset without PCIRST enable (CRst_En)
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* 1 = Enable
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* 0 = Disable
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*/
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/* Enable normal refresh and the gated clock. */
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// TODO: Only do this later?
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// PMCR, 0x00, 0x14,
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// PMCR, 0x00, 0x10,
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PMCR, 0x00, 0x00,
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/* Enable SCRR.SRRAEN and let BX choose the SRR. */
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SCRR + 1, 0x00, 0x10,
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};
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/*-----------------------------------------------------------------------------
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SDRAM configuration functions.
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-----------------------------------------------------------------------------*/
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/**
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* Send the specified RAM command to all DIMMs.
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*
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* @param command The RAM command to send to the DIMM(s).
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*/
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static void do_ram_command(u32 command)
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{
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int i, caslatency;
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u8 dimm_start, dimm_end;
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u16 reg16;
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u32 addr, addr_offset;
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/* Configure the RAM command. */
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reg16 = pci_read_config16(NB, SDRAMC);
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reg16 &= 0xff1f; /* Clear bits 7-5. */
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reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */
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pci_write_config16(NB, SDRAMC, reg16);
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/*
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* RAM_COMMAND_NORMAL affects only the memory controller and
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* doesn't need to be "sent" to the DIMMs.
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*/
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if (command == RAM_COMMAND_NORMAL)
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return;
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/* Send the RAM command to each row of memory. */
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dimm_start = 0;
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for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
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addr_offset = 0;
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caslatency = 3; /* TODO: Dynamically get CAS latency later. */
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if (command == RAM_COMMAND_MRS) {
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/*
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* MAA[12:11,9:0] must be inverted when sent to DIMM
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* 2 or 3 (no inversion if sent to DIMM 0 or 1).
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*/
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if ((i >= 0 && i <= 3) && caslatency == 3)
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addr_offset = 0x1d0;
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if ((i >= 4 && i <= 7) && caslatency == 3)
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addr_offset = 0x1e28;
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if ((i >= 0 && i <= 3) && caslatency == 2)
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addr_offset = 0x150;
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if ((i >= 4 && i <= 7) && caslatency == 2)
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addr_offset = 0x1ea8;
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}
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dimm_end = pci_read_config8(NB, DRB + i);
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addr = (dimm_start * 8 * 1024 * 1024) + addr_offset;
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if (dimm_end > dimm_start) {
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#if 0
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PRINT_DEBUG(" Sending RAM command 0x");
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PRINT_DEBUG_HEX16(reg16);
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PRINT_DEBUG(" to 0x");
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PRINT_DEBUG_HEX32(addr);
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PRINT_DEBUG("\n");
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#endif
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read32(addr);
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}
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/* Set the start of the next DIMM. */
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dimm_start = dimm_end;
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}
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}
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static void set_dram_buffer_strength(void)
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{
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/* To give some breathing room for romcc,
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* mbsc0 doubles as drb
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* mbsc1 doubles as drb1
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* mbfs0 doubles as i and reg
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*/
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uint8_t mbsc0,mbsc1,mbsc3,mbsc4,mbfs0,mbfs2,fsb;
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/* Tally how many rows between rows 0-3 and rows 4-7 are populated.
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* This determines how to program MBFS and MBSC.
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*/
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uint8_t dimm03 = 0;
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uint8_t dimm47 = 0;
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mbsc0 = 0;
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for (mbfs0 = DRB0; mbfs0 <= DRB7; mbfs0++) {
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mbsc1 = pci_read_config8(NB, mbfs0);
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if (mbsc0 != mbsc1) {
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if (mbfs0 <= DRB3) {
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dimm03++;
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} else {
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dimm47++;
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}
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mbsc0 = mbsc1;
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}
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}
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/* Algorithm bitmap for programming MBSC[39:0] and MBFS[23:0]
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*
|
|
* 440BX datasheet says buffer frequency is independent from bus frequency
|
|
* and mismatch both ways are possible. This is how it is programmed
|
|
* in ASUS P2B-LS.
|
|
*
|
|
* There are four main conditions to check when programming DRAM buffer
|
|
* frequency and strength:
|
|
*
|
|
* a: >2 rows populated across DIMM0,1
|
|
* b: >2 rows populated across DIMM2,3
|
|
* c: >4 rows populated across all DIMM slots
|
|
* and either one of:
|
|
* 1: NBXCFG[13] strapped as 100MHz, or
|
|
* 6: NBXCFG[13] strapped as 66MHz
|
|
*
|
|
* CKE0/FENA ----------------------------------------------------------+
|
|
* CKE1/GCKE -------------------[ MBFS ]------------------------+|
|
|
* DQMA/CASA[764320]# ----------[ 0 = 66MHz ]-----------------------+||
|
|
* DQMB1/CASB1# ----------------[ 1 = 100MHz ]----------------------+|||
|
|
* DQMB5/CASB5# ---------------------------------------------------+||||
|
|
* DQMA1/CASA1# --------------------------------------------------+|||||
|
|
* DQMA5/CASA5# -------------------------------------------------+||||||
|
|
* CSA0-5#,CSB0-5# ----------------------------------------++++++|||||||
|
|
* CSA6#/CKE2# -------------------------------------------+|||||||||||||
|
|
* CSB6#/CKE4# ------------------------------------------+||||||||||||||
|
|
* CSA7#/CKE3# -----------------------------------------+|||||||||||||||
|
|
* CSB7#/CKE5# ----------------------------------------+||||||||||||||||
|
|
* MECC[7:0] #2/#1 (100MHz) -------------------------++|||||||||||||||||
|
|
* MD[63:0] #2/#1 (100MHz) ------------------------++|||||||||||||||||||
|
|
* MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||
|
|
* MAA[13:0],WEA#,SRASA#,SCASA# -----------------+||||||||||||||||||||||
|
|
* Reserved ------------------------------------+|||||||||||||||||||||||
|
|
* ||||||||||||||||||||||||
|
|
* 3 32 21 10 0 * 2 21 10 0
|
|
* 9876543210987654321098765432109876543210 * 321098765432109876543210
|
|
* a 10------------------------1010---------- * -1---------------11----- a
|
|
*!a 11------------------------1111---------- * -0---------------00----- !a
|
|
* b --10--------------------------1010------ * --1----------------11--- b
|
|
*!b --11--------------------------1111------ * --0----------------00--- !b
|
|
* c ----------------------------------1100-- * ----------------------1- c
|
|
*!c ----------------------------------1011-- * ----------------------0- !c
|
|
* 1 ----1010101000000000000000------------00 * ---11111111111111----1-0 1
|
|
* 6 ----000000000000000000000010101010----00 * ---1111111111111100000-0 6
|
|
* | | | | | | | | | | ||||||| | | | | | |
|
|
* | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA
|
|
* | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE
|
|
* | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#
|
|
* | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1#
|
|
* | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5#
|
|
* | | | | | | | | | | ||||||| +----------- DQMA1/CASA1#
|
|
* | | | | | | | | | | ||||||+------------- DQMA5/CASA5#
|
|
* | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# [ 0=1x;1=2x ]
|
|
* | | | | | | | | | +--------------------- CSA6#/CKE2#
|
|
* | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4#
|
|
* | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3#
|
|
* | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5#
|
|
* | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (2x)
|
|
* | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (2x)
|
|
* | | | +--------------------------------- MD[63:0] #1 (2x)
|
|
* | | +----------------------------------- MD[63:0] #2 (2x)
|
|
* | +------------------------------------- MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#
|
|
* +--------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
|
|
* MBSC[47:40] and MBFS[23] are reserved.
|
|
*
|
|
* This algorithm is checked against P2B-LS factory BIOS. It has 4 DIMM slots.
|
|
* Therefore it assumes a board with 4 slots, and will need testing
|
|
* on boards with 3 DIMM slots.
|
|
*/
|
|
|
|
mbsc0 = 0x80;
|
|
mbsc1 = 0x2a;
|
|
mbfs2 = 0x1f;
|
|
if (pci_read_config8(NB, NBXCFG + 1) & 0x30) {
|
|
fsb = 66;
|
|
mbsc3 = 0x00;
|
|
mbsc4 = 0x00;
|
|
mbfs0 = 0x80;
|
|
} else {
|
|
fsb = 100;
|
|
mbsc3 = 0xa0;
|
|
mbsc4 = 0x0a;
|
|
mbfs0 = 0x84;
|
|
}
|
|
|
|
if (dimm03 > 2) {
|
|
mbsc4 = mbsc4 | 0x80;
|
|
mbsc1 = mbsc1 | 0x28;
|
|
mbfs2 = mbfs2 | 0x40;
|
|
mbfs0 = mbfs0 | 0x60;
|
|
} else {
|
|
mbsc4 = mbsc4 | 0xc0;
|
|
if (fsb == 100) {
|
|
mbsc1 = mbsc1 | 0x3c;
|
|
}
|
|
}
|
|
if (dimm47 > 2) {
|
|
mbsc4 = mbsc4 | 0x20;
|
|
mbsc1 = mbsc1 | 0x02;
|
|
mbsc0 = mbsc0 | 0x80;
|
|
mbfs2 = mbfs2 | 0x20;
|
|
mbfs0 = mbfs0 | 0x18;
|
|
} else {
|
|
mbsc4 = mbsc4 | 0x30;
|
|
if (fsb == 100) {
|
|
mbsc1 = mbsc1 | 0x03;
|
|
mbsc0 = mbsc0 | 0xc0;
|
|
}
|
|
}
|
|
if ((dimm03 + dimm47) > 4) {
|
|
mbsc0 = mbsc0 | 0x30;
|
|
mbfs0 = mbfs0 | 0x02;
|
|
} else {
|
|
mbsc0 = mbsc0 | 0x2c;
|
|
}
|
|
|
|
pci_write_config8(NB, MBSC + 0, mbsc0);
|
|
pci_write_config8(NB, MBSC + 1, mbsc1);
|
|
pci_write_config8(NB, MBSC + 2, 0x00);
|
|
pci_write_config8(NB, MBSC + 3, mbsc3);
|
|
pci_write_config8(NB, MBSC + 4, mbsc4);
|
|
pci_write_config8(NB, MBFS + 0, mbfs0);
|
|
pci_write_config8(NB, MBFS + 1, 0xff);
|
|
pci_write_config8(NB, MBFS + 2, mbfs2);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------------
|
|
DIMM-independant configuration functions.
|
|
-----------------------------------------------------------------------------*/
|
|
|
|
static void spd_enable_refresh(void)
|
|
{
|
|
int i, value;
|
|
uint8_t reg;
|
|
|
|
reg = pci_read_config8(NB, DRAMC);
|
|
|
|
for (i = 0; i < DIMM_SOCKETS; i++) {
|
|
value = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH);
|
|
if (value < 0)
|
|
continue;
|
|
reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
|
|
|
|
PRINT_DEBUG(" Enabling refresh (DRAMC = 0x");
|
|
PRINT_DEBUG_HEX8(reg);
|
|
PRINT_DEBUG(") for DIMM ");
|
|
PRINT_DEBUG_HEX8(i);
|
|
PRINT_DEBUG("\n");
|
|
}
|
|
|
|
pci_write_config8(NB, DRAMC, reg);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------------
|
|
Public interface.
|
|
-----------------------------------------------------------------------------*/
|
|
|
|
static void sdram_set_registers(void)
|
|
{
|
|
int i, max;
|
|
uint8_t reg;
|
|
|
|
PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
|
|
DUMPNORTH();
|
|
|
|
max = ARRAY_SIZE(register_values);
|
|
|
|
/* Set registers as specified in the register_values[] array. */
|
|
for (i = 0; i < max; i += 3) {
|
|
reg = pci_read_config8(NB, register_values[i]);
|
|
reg &= register_values[i + 1];
|
|
reg |= register_values[i + 2] & ~(register_values[i + 1]);
|
|
pci_write_config8(NB, register_values[i], reg);
|
|
#if 0
|
|
PRINT_DEBUG(" Set register 0x");
|
|
PRINT_DEBUG_HEX8(register_values[i]);
|
|
PRINT_DEBUG(" to 0x");
|
|
PRINT_DEBUG_HEX8(reg);
|
|
PRINT_DEBUG("\n");
|
|
#endif
|
|
}
|
|
}
|
|
|
|
struct dimm_size {
|
|
unsigned long side1;
|
|
unsigned long side2;
|
|
};
|
|
|
|
static struct dimm_size spd_get_dimm_size(unsigned int device)
|
|
{
|
|
struct dimm_size sz;
|
|
int i, module_density, dimm_banks;
|
|
sz.side1 = 0;
|
|
module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
|
|
dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
|
|
|
|
/* Find the size of side1. */
|
|
/* Find the larger value. The larger value is always side1. */
|
|
for (i = 512; i >= 0; i >>= 1) {
|
|
if ((module_density & i) == i) {
|
|
sz.side1 = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Set to 0 in case it's single sided. */
|
|
sz.side2 = 0;
|
|
|
|
/* Test if it's a dual-sided DIMM. */
|
|
if (dimm_banks > 1) {
|
|
/* Test if there's a second value. If so it's asymmetrical. */
|
|
if (module_density != i) {
|
|
/*
|
|
* Find second value, picking up where we left off.
|
|
* i >>= 1 done initially to make sure we don't get
|
|
* the same value again.
|
|
*/
|
|
for (i >>= 1; i >= 0; i >>= 1) {
|
|
if (module_density == (sz.side1 | i)) {
|
|
sz.side2 = i;
|
|
break;
|
|
}
|
|
}
|
|
/* If not, it's symmetrical. */
|
|
} else {
|
|
sz.side2 = sz.side1;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* SPD byte 31 is the memory size divided by 4 so we
|
|
* need to muliply by 4 to get the total size.
|
|
*/
|
|
sz.side1 *= 4;
|
|
sz.side2 *= 4;
|
|
|
|
return sz;
|
|
}
|
|
/*
|
|
* Sets DRAM attributes one DIMM at a time, based on SPD data.
|
|
* Northbridge settings that are set: NBXCFG[31:24], DRB0-DRB7, RPS, DRAMC.
|
|
*/
|
|
static void set_dram_row_attributes(void)
|
|
{
|
|
int i, dra, drb, col, width, value, rps, edosd, ecc, nbxecc;
|
|
u8 bpr; /* Top 8 bits of PGPOL */
|
|
|
|
edosd = 0;
|
|
rps = 0;
|
|
drb = 0;
|
|
bpr = 0;
|
|
nbxecc = 0xff;
|
|
|
|
for (i = 0; i < DIMM_SOCKETS; i++) {
|
|
unsigned int device;
|
|
device = DIMM_SPD_BASE + i;
|
|
bpr >>= 2;
|
|
|
|
/* First check if a DIMM is actually present. */
|
|
value = spd_read_byte(device, SPD_MEMORY_TYPE);
|
|
/* This is 440BX! We do EDO too! */
|
|
if (value == SPD_MEMORY_TYPE_EDO
|
|
|| value == SPD_MEMORY_TYPE_SDRAM) {
|
|
|
|
PRINT_DEBUG("Found ");
|
|
if (value == SPD_MEMORY_TYPE_EDO) {
|
|
edosd |= 0x02;
|
|
} else if (value == SPD_MEMORY_TYPE_SDRAM) {
|
|
edosd |= 0x04;
|
|
}
|
|
PRINT_DEBUG("DIMM in slot ");
|
|
PRINT_DEBUG_HEX8(i);
|
|
PRINT_DEBUG("\n");
|
|
|
|
if (edosd == 0x06) {
|
|
print_err("Mixing EDO/SDRAM unsupported!\n");
|
|
die("HALT\n");
|
|
}
|
|
|
|
/* "DRA" is our RPS for the two rows on this DIMM. */
|
|
dra = 0;
|
|
|
|
/* Columns */
|
|
col = spd_read_byte(device, SPD_NUM_COLUMNS);
|
|
|
|
/*
|
|
* Is this an ECC DIMM? Actually will be a 2 if so.
|
|
* TODO: Other register than NBXCFG also needs this
|
|
* ECC information.
|
|
*/
|
|
ecc = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
|
|
|
|
/* Data width */
|
|
width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
|
|
|
|
/* Exclude error checking data width from page size calculations */
|
|
if (ecc) {
|
|
value = spd_read_byte(device,
|
|
SPD_ERROR_CHECKING_SDRAM_WIDTH);
|
|
width -= value;
|
|
/* ### ECC */
|
|
/* Clear top 2 bits to help set up NBXCFG. */
|
|
ecc &= 0x3f;
|
|
} else {
|
|
/* Without ECC, top 2 bits should be 11. */
|
|
ecc |= 0xc0;
|
|
}
|
|
|
|
/* Calculate page size in bits. */
|
|
value = ((1 << col) * width);
|
|
|
|
/* Convert to KB. */
|
|
dra = (value >> 13);
|
|
|
|
/* Number of banks of DIMM (single or double sided). */
|
|
value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
|
|
|
|
/* Once we have dra, col is done and can be reused.
|
|
* So it's reused for number of banks.
|
|
*/
|
|
col = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM);
|
|
|
|
if (value == 1) {
|
|
/*
|
|
* Second bank of 1-bank DIMMs "doesn't have
|
|
* ECC" - or anything.
|
|
*/
|
|
ecc |= 0x80;
|
|
if (dra == 2) {
|
|
dra = 0x0; /* 2KB */
|
|
} else if (dra == 4) {
|
|
dra = 0x1; /* 4KB */
|
|
} else if (dra == 8) {
|
|
dra = 0x2; /* 8KB */
|
|
} else {
|
|
dra = -1;
|
|
}
|
|
/*
|
|
* Sets a flag in PGPOL[BPR] if this DIMM has
|
|
* 4 banks per row.
|
|
*/
|
|
if (col == 4)
|
|
bpr |= 0x40;
|
|
} else if (value == 2) {
|
|
if (dra == 2) {
|
|
dra = 0x0; /* 2KB */
|
|
} else if (dra == 4) {
|
|
dra = 0x05; /* 4KB */
|
|
} else if (dra == 8) {
|
|
dra = 0x0a; /* 8KB */
|
|
} else {
|
|
dra = -1;
|
|
}
|
|
/* Ditto */
|
|
if (col == 4)
|
|
bpr |= 0xc0;
|
|
} else {
|
|
print_err("# of banks of DIMM unsupported!\n");
|
|
die("HALT\n");
|
|
}
|
|
if (dra == -1) {
|
|
print_err("Page size not supported\n");
|
|
die("HALT\n");
|
|
}
|
|
|
|
/*
|
|
* 440BX supports asymmetrical dual-sided DIMMs,
|
|
* but can't handle DIMMs smaller than 8MB per
|
|
* side or larger than 128MB per side.
|
|
*/
|
|
struct dimm_size sz = spd_get_dimm_size(device);
|
|
if ((sz.side1 < 8)) {
|
|
print_err("DIMMs smaller than 8MB per side\n"
|
|
"are not supported on this NB.\n");
|
|
die("HALT\n");
|
|
}
|
|
if ((sz.side1 > 128)) {
|
|
print_err("DIMMs > 128MB per side\n"
|
|
"are not supported on this NB\n");
|
|
die("HALT\n");
|
|
}
|
|
|
|
/* Divide size by 8 to set up the DRB registers. */
|
|
drb += (sz.side1 / 8);
|
|
|
|
/*
|
|
* Build the DRB for the next row in MSB so it gets
|
|
* placed in DRB[n+1] where it belongs when written
|
|
* as a 16-bit word.
|
|
*/
|
|
drb &= 0xff;
|
|
drb |= (drb + (sz.side2 / 8)) << 8;
|
|
} else {
|
|
#if 0
|
|
PRINT_DEBUG("No DIMM found in slot ");
|
|
PRINT_DEBUG_HEX8(i);
|
|
PRINT_DEBUG("\n");
|
|
#endif
|
|
|
|
/* If there's no DIMM in the slot, set dra to 0x00. */
|
|
dra = 0x00;
|
|
ecc = 0xc0;
|
|
/* Still have to propagate DRB over. */
|
|
drb &= 0xff;
|
|
drb |= (drb << 8);
|
|
}
|
|
|
|
pci_write_config16(NB, DRB + (2 * i), drb);
|
|
#if 0
|
|
PRINT_DEBUG("DRB has been set to 0x");
|
|
PRINT_DEBUG_HEX16(drb);
|
|
PRINT_DEBUG("\n");
|
|
#endif
|
|
|
|
/* Brings the upper DRB back down to be base for
|
|
* DRB calculations for the next two rows.
|
|
*/
|
|
drb >>= 8;
|
|
|
|
rps |= (dra & 0x0f) << (i * 4);
|
|
nbxecc = (nbxecc >> 2) | (ecc & 0xc0);
|
|
}
|
|
|
|
/* Set paging policy register. */
|
|
pci_write_config8(NB, PGPOL + 1, bpr);
|
|
PRINT_DEBUG("PGPOL[BPR] has been set to 0x");
|
|
PRINT_DEBUG_HEX8(bpr);
|
|
PRINT_DEBUG("\n");
|
|
|
|
/* Set DRAM row page size register. */
|
|
pci_write_config16(NB, RPS, rps);
|
|
PRINT_DEBUG("RPS has been set to 0x");
|
|
PRINT_DEBUG_HEX16(rps);
|
|
PRINT_DEBUG("\n");
|
|
|
|
/* ### ECC */
|
|
pci_write_config8(NB, NBXCFG + 3, nbxecc);
|
|
PRINT_DEBUG("NBXECC[31:24] has been set to 0x");
|
|
PRINT_DEBUG_HEX8(nbxecc);
|
|
PRINT_DEBUG("\n");
|
|
|
|
/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM).
|
|
* TODO: Registered SDRAM support.
|
|
*/
|
|
edosd &= 0x07;
|
|
if (edosd & 0x02) {
|
|
edosd |= 0x00;
|
|
} else if (edosd & 0x04) {
|
|
edosd |= 0x08;
|
|
}
|
|
edosd &= 0x18;
|
|
|
|
/* edosd is now in the form needed for DRAMC[4:3]. */
|
|
value = pci_read_config8(NB, DRAMC) & 0xe7;
|
|
value |= edosd;
|
|
pci_write_config8(NB, DRAMC, value);
|
|
PRINT_DEBUG("DRAMC has been set to 0x");
|
|
PRINT_DEBUG_HEX8(value);
|
|
PRINT_DEBUG("\n");
|
|
}
|
|
|
|
static void sdram_set_spd_registers(void)
|
|
{
|
|
/* Setup DRAM row boundary registers and other attributes. */
|
|
set_dram_row_attributes();
|
|
|
|
/* TODO: Set SDRAMC. */
|
|
pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */
|
|
|
|
/* TODO */
|
|
set_dram_buffer_strength();
|
|
|
|
/* TODO: Set PMCR? */
|
|
// pci_write_config8(NB, PMCR, 0x14);
|
|
pci_write_config8(NB, PMCR, 0x10);
|
|
|
|
/* TODO? */
|
|
pci_write_config8(NB, DRAMT, 0x03);
|
|
}
|
|
|
|
static void sdram_enable(void)
|
|
{
|
|
int i;
|
|
|
|
/* 0. Wait until power/voltages and clocks are stable (200us). */
|
|
udelay(200);
|
|
|
|
/* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
|
|
PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
|
|
do_ram_command(RAM_COMMAND_NOP);
|
|
udelay(200);
|
|
|
|
/* 2. Precharge all. Wait tRP. */
|
|
PRINT_DEBUG("RAM Enable 2: Precharge all\n");
|
|
do_ram_command(RAM_COMMAND_PRECHARGE);
|
|
udelay(1);
|
|
|
|
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
|
|
PRINT_DEBUG("RAM Enable 3: CBR\n");
|
|
for (i = 0; i < 8; i++) {
|
|
do_ram_command(RAM_COMMAND_CBR);
|
|
udelay(1);
|
|
}
|
|
|
|
/* 4. Mode register set. Wait two memory cycles. */
|
|
PRINT_DEBUG("RAM Enable 4: Mode register set\n");
|
|
do_ram_command(RAM_COMMAND_MRS);
|
|
udelay(2);
|
|
|
|
/* 5. Normal operation. */
|
|
PRINT_DEBUG("RAM Enable 5: Normal operation\n");
|
|
do_ram_command(RAM_COMMAND_NORMAL);
|
|
udelay(1);
|
|
|
|
/* 6. Finally enable refresh. */
|
|
PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
|
|
// pci_write_config8(NB, PMCR, 0x10);
|
|
spd_enable_refresh();
|
|
udelay(1);
|
|
|
|
PRINT_DEBUG("Northbridge following SDRAM init:\n");
|
|
DUMPNORTH();
|
|
}
|