0f007d8ceb
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
134 lines
3.2 KiB
C
134 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <types.h>
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#include <console/console.h>
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#include <commonlib/helpers.h>
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#include <arch/acpi.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include "sandybridge.h"
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#include <southbridge/intel/bd82x6x/pch.h>
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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u32 pciexbar = 0;
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u32 pciexbar_reg;
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int max_buses;
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struct device *const dev = pcidev_on_root(0, 0);
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if (!dev)
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return current;
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pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
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/* MMCFG not supported or not enabled */
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if (!(pciexbar_reg & (1 << 0)))
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return current;
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: /* 256MB */
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pciexbar = pciexbar_reg & (0xffffffffULL << 28);
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max_buses = 256;
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break;
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case 1: /* 128M */
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pciexbar = pciexbar_reg & (0xffffffffULL << 27);
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max_buses = 128;
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break;
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case 2: /* 64M */
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pciexbar = pciexbar_reg & (0xffffffffULL << 26);
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max_buses = 64;
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break;
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default: /* RSVD */
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return current;
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}
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if (!pciexbar)
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return current;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
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max_buses - 1);
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return current;
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}
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static unsigned long acpi_create_igfx_rmrr(const unsigned long current)
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{
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const u32 base_mask = ~(u32)(MiB - 1);
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struct device *const host = pcidev_on_root(0, 0);
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if (!host)
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return 0;
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const u32 bgsm = pci_read_config32(host, BGSM) & base_mask;
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const u32 tolud = pci_read_config32(host, TOLUD) & base_mask;
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if (!bgsm || !tolud)
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return 0;
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return acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1);
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}
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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const struct device *const igfx = pcidev_on_root(2, 0);
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if (igfx && igfx->enabled) {
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unsigned long tmp;
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tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 1);
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acpi_dmar_drhd_fixup(tmp, current);
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tmp = current;
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current += acpi_create_igfx_rmrr(current);
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if (current != tmp) {
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 1);
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acpi_dmar_rmrr_fixup(tmp, current);
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}
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}
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);
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current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
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PCH_IOAPIC_PCI_SLOT, 0);
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size_t i;
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for (i = 0; i < 8; ++i)
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current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS,
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PCH_HPET_PCI_SLOT, i);
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acpi_dmar_drhd_fixup(tmp, current);
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return current;
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}
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unsigned long northbridge_write_acpi_tables(const struct device *const dev,
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unsigned long current,
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struct acpi_rsdp *const rsdp)
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{
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const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
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if (capid0_a & (1 << 23))
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return current;
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
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acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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current = acpi_align_current(current);
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printk(BIOS_DEBUG, "current = %lx\n", current);
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return current;
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}
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