0f49bbceef
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
82 lines
2.4 KiB
C
82 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/intel/broadwell/chip.h>
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static void pci_domain_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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.ops_pci_bus = &pci_bus_default_ops,
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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.write_acpi_tables = &northbridge_write_acpi_tables,
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#endif
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};
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static struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = &broadwell_init_cpus,
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};
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static void broadwell_enable(device_t dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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} else if (dev->path.type == DEVICE_PATH_PCI) {
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/* Handle PCH device enable */
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if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD &&
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(dev->ops == NULL || dev->ops->enable == NULL)) {
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broadwell_pch_enable_dev(dev);
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}
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}
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}
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struct chip_operations soc_intel_broadwell_ops = {
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CHIP_NAME("Intel Broadwell")
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.enable_dev = &broadwell_enable,
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.init = &broadwell_init_pre_device,
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};
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static void pci_set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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if (!vendor || !device)
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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else
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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(device << 16) | vendor);
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}
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struct pci_operations broadwell_pci_ops = {
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.set_subsystem = &pci_set_subsystem
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};
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