0f593c22a8
Apollolake defines Global Reset where Host, TXE and PMC are reset. During boot we may need to trigger a global reset as part of platform initialization (or for error handling). Add functions to trigger global reset, enable/disable it and lock global reset bit. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
107 lines
3.1 KiB
Makefile
107 lines
3.1 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cache_as_ram.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += car.c
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bootblock-y += gpio.c
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bootblock-y += lpc_lib.c
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bootblock-y += mmap_boot.c
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bootblock-y += spi.c
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bootblock-y += tsc_freq.c
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bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += car.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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romstage-y += gpio.c
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romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += lpc_lib.c
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romstage-y += memmap.c
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romstage-y += meminit.c
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romstage-y += mmap_boot.c
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romstage-y += tsc_freq.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += spi.c
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smm-y += mmap_boot.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += spi.c
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smm-y += tsc_freq.c
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smm-y += uart_early.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += cpu.c
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ramstage-y += chip.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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ramstage-y += lpc.c
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ramstage-y += lpc_lib.c
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ramstage-y += memmap.c
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ramstage-y += mmap_boot.c
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ramstage-y += uart.c
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ramstage-y += northbridge.c
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ramstage-y += spi.c
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ramstage-y += tsc_freq.c
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ramstage-y += pmutil.c
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ramstage-y += pmc.c
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ramstage-y += reset.c
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ramstage-y += smi.c
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ramstage-y += spi.c
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postcar-y += exit_car.S
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postcar-y += memmap.c
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postcar-y += mmap_boot.c
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postcar-y += spi.c
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postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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postcar-y += tsc_freq.c
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verstage-y += car.c
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verstage-y += memmap.c
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verstage-y += mmap_boot.c
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verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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verstage-y += tsc_freq.c
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verstage-y += pmutil.c
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verstage-y += reset.c
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verstage-y += spi.c
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CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
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# Since FSP-M runs in CAR we need to relocate it to a specific address
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$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
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ifeq ($(CONFIG_NEED_LBP2),y)
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files_added::
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$(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward
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endif
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# Bootblock on Apollolake platform lies in the IFWI region. In order to place
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# the bootblock at the right location in IFWI image -
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# a. Using ifwitool:
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# 1. Create IFWI image (ifwi.bin.tmp) from input image
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# (CONFIG_IFWI_FILE_NAME).
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# 2. Delete OBBP sub-partition, if present.
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# 3. Replace IBBL directory entry in IBBP sub-partition with currently
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# generated bootblock.bin.
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# b. Using cbfstool:
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# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME.
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ifeq ($(CONFIG_NEED_IFWI),y)
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files_added:: $(IFWITOOL)
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$(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp
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$(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP
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$(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL
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$(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward
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endif
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endif
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