7dcf9d51e5
This patch removes the old arm64/stage_entry.S code that was too specific to the Tegra SoC boot flow, and replaces it with code that hides the peculiarities of switching to a different CPU/arch in ramstage in the Tegra SoC directories. BRANCH=None BUG=None TEST=Built Ryu and Smaug. !!!UNTESTED!!! Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12078 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
130 lines
3.9 KiB
C
130 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cache.h>
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#include <arch/lib_helpers.h>
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#include <arch/transition.h>
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#include <assert.h>
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#include <console/console.h>
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/* Litte-endian, No XN-forced, Instr cache disabled,
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* Stack alignment disabled, Data and unified cache
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* disabled, Alignment check disabled, MMU disabled
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*/
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#define SCTLR_MASK (SCTLR_MMU_DISABLE | SCTLR_ACE_DISABLE | \
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SCTLR_CACHE_DISABLE | SCTLR_SAE_DISABLE | SCTLR_RES1 | \
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SCTLR_ICE_DISABLE | SCTLR_WXN_DISABLE | SCTLR_LITTLE_END)
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void __attribute__((weak)) exc_dispatch(struct exc_state *exc_state, uint64_t id)
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{
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/* Default weak implementation does nothing. */
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}
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void exc_entry(struct exc_state *exc_state, uint64_t id)
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{
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struct elx_state *elx = &exc_state->elx;
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struct regs *regs = &exc_state->regs;
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uint8_t elx_mode, elx_el;
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elx->spsr = raw_read_spsr_current();
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elx_mode = get_mode_from_spsr(elx->spsr);
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elx_el = get_el_from_spsr(elx->spsr);
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if (elx_mode == SPSR_USE_H) {
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if (elx_el == get_current_el())
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regs->sp = (uint64_t)&exc_state[1];
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else
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regs->sp = raw_read_sp_elx(elx_el);
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} else {
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regs->sp = raw_read_sp_el0();
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}
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elx->elr = raw_read_elr_current();
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exc_dispatch(exc_state, id);
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}
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void transition_with_entry(void *entry, void *arg, struct exc_state *exc_state)
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{
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/* Argument to entry point goes into X0 */
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exc_state->regs.x[X0_INDEX] = (uint64_t)arg;
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/* Entry point goes into ELR */
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exc_state->elx.elr = (uint64_t)entry;
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transition(exc_state);
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}
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void transition(struct exc_state *exc_state)
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{
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uint64_t sctlr;
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uint32_t current_el = get_current_el();
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struct elx_state *elx = &exc_state->elx;
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struct regs *regs = &exc_state->regs;
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uint8_t elx_el = get_el_from_spsr(elx->spsr);
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/*
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* Policies enforced:
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* 1. We support only elx --> (elx - 1) transitions
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* 2. We support transitions to Aarch64 mode only
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*
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* If any of the above conditions holds false, then we need a proper way
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* to update SCR/HCR before removing the checks below
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*/
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if ((current_el - elx_el) != 1)
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die("ARM64 Error: Do not support transition\n");
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if (elx->spsr & SPSR_ERET_32)
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die("ARM64 Error: Do not support eret to Aarch32\n");
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/* Most parts of coreboot currently don't support EL2 anyway. */
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assert(current_el == EL3);
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/* Initialize SCR with defaults for running without secure monitor. */
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raw_write_scr_el3(SCR_TWE_DISABLE | /* don't trap WFE */
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SCR_TWI_DISABLE | /* don't trap WFI */
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SCR_ST_ENABLE | /* allow secure timer access */
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SCR_LOWER_AARCH64 | /* lower level is AArch64 */
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SCR_SIF_DISABLE | /* disable secure ins. fetch */
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SCR_HVC_ENABLE | /* allow HVC instruction */
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SCR_SMD_ENABLE | /* disable SMC instruction */
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SCR_RES1 | /* reserved-1 bits */
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SCR_EA_DISABLE | /* disable ext. abort trap */
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SCR_FIQ_DISABLE | /* disable FIQ trap to EL3 */
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SCR_IRQ_DISABLE | /* disable IRQ trap to EL3 */
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SCR_NS_ENABLE); /* lower level is non-secure */
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/* Initialize CPTR to not trap anything to EL3. */
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raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE |
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CPTR_EL3_TFP_DISABLE);
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/* ELR/SPSR: Write entry point and processor state of program */
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raw_write_elr_current(elx->elr);
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raw_write_spsr_current(elx->spsr);
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/* SCTLR: Initialize EL with selected properties */
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sctlr = raw_read_sctlr(elx_el);
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sctlr &= SCTLR_MASK;
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raw_write_sctlr(sctlr, elx_el);
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/* SP_ELx: Initialize stack pointer */
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raw_write_sp_elx(elx->sp_elx, elx_el);
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isb();
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/* Eret to the entry point */
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trans_switch(regs);
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}
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