0fd8ccd7e7
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
127 lines
3.4 KiB
C
Executable File
127 lines
3.4 KiB
C
Executable File
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <stdlib.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "pc80/udelay_io.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
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#include "northbridge/intel/i82830/raminit.h"
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#include "northbridge/intel/i82830/memory_initialized.c"
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#include "southbridge/intel/i82801xx/i82801xx.h"
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#include "southbridge/intel/i82801xx/i82801xx_reset.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "spd_table.h"
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#include "gpio.c"
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#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
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#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
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#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
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/**
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* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
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* values have to be set manually, the SO-DIMM socket is located in
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* socket0 (0x50), and the onboard memory is located in socket1 (0x51).
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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int i;
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if (device == 0x50) {
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return smbus_read_byte(device, address);
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} else if (device == 0x51) {
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for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
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if (spd_table[i].address == address)
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return spd_table[i].data;
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}
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return 0xFF; /* Return 0xFF when address is not found. */
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} else {
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return 0xFF; /* Return 0xFF on any failures. */
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}
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}
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#include "northbridge/intel/i82830/raminit.c"
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#include "sdram/generic_sdram.c"
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/**
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* The AC'97 Audio Controller I/O space registers are read only by default
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* so we need to enable them by setting register 0x41 to 0x01.
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*/
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static void ac97_io_enable(void)
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{
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device_t dev;
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/* Set the ac97 audio device staticly. */
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dev = PCI_DEV(0x0, 0x1f, 0x5);
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/* Enable access to the IO space. */
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pci_write_config8(dev, 0x41, 0x01);
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}
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 0),
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.channel0 = {0x50, 0x51},
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}
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};
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if (bist == 0)
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early_mtrr_init();
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if (memory_initialized()) {
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hard_reset();
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}
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enable_smbus();
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smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
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mb_gpio_init();
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uart_init();
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console_init();
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/* Prevent the TCO timer from rebooting us */
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i82801xx_halt_tco_timer();
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/* Halt if there was a built in self test failure. */
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report_bist_failure(bist);
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sdram_set_registers(memctrl);
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sdram_set_spd_registers(memctrl);
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sdram_enable(0, memctrl);
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/* Check RAM. */
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/* ram_check(0, 640 * 1024); */
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/* ram_check(64512 * 1024, 65536 * 1024); */
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ac97_io_enable();
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}
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