0fdd9fd2aa
Change-Id: I8930e96e5f2c45b8658dc4dfe1ab57d573e7b26f
Fixes: b75bcc978a ("mb/ocp/tiogapass: Properly configure early serial output")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <bootblock_common.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <intelblocks/pcr.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <superio/aspeed/common/aspeed.h>
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/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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static void enable_espi_lpc_io_windows(void)
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{
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/*
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* Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
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* one is connected to debug header (SUART1) and another is used as SOL (SUART2).
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* For that end it is wired into BMC virtual port.
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*/
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/* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4));
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/* LPC I/O enable: com1 and com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1));
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/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
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pci_mmio_write_config32(PCH_DEV_LPC, 0x80,
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(1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4));
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}
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static uint8_t com_to_ast_sio(uint8_t com)
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{
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switch (com) {
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case 0:
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return AST2400_SUART1;
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case 1:
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return AST2400_SUART2;
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case 2:
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return AST2400_SUART3;
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case 4:
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return AST2400_SUART4;
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default:
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return AST2400_SUART1;
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}
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}
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void bootblock_mainboard_early_init(void)
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{
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/* Open IO windows */
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enable_espi_lpc_io_windows();
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/* Configure appropriate physical port of SuperIO chip off BMC */
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const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
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aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
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}
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