0ffff3434e
EPIA-M700 target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
238 lines
8.1 KiB
C
238 lines
8.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 One Laptop per Child, Association, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "northbridge/via/vx800/DrivingClkPhaseData.h"
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// DQS Driving
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// Reg0xE0, 0xE1
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// According to #Bank to set DRAM DQS Driving
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// #Bank 1 2 3 4 5 6 7 8
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static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE };
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static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE };
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// DQ Driving
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// Reg0xE2, 0xE3
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// For DDR2: According to bank to set DRAM DQ Driving
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static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC };
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static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA };
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// CS Driving
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// Reg0xE4, 0xE5
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// According to #Bank to set DRAM CS Driving
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// DDR1 #Bank 1 2 3 4 5 6 7 8
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static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 };
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static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44 };
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static const u8 DDR2_CSA_Driving_Table_x16[4] = { 0x44, 0x44, 0x44, 0x44 };
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static const u8 DDR2_CSB_Driving_Table_x16[2] = { 0x44, 0x44 };
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// MAA Driving
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// Reg0xE8, Reg0xE9
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static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = {
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// Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8
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{6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06
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{18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18
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{255, 0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~
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};
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static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = {
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// Chip number, Value ;(SRAS, SCAS, SWE)RxE9
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{6, 0x86}, // total MAB chips = 00 ~ 06
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{18, 0x86}, // total MAB chips = 06 ~ 18
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{255, 0xDB}, // total MAB chips = 18 ~
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};
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// DCLK Driving
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// Reg0xE6, 0xE7
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// For DDR2: According to #Freq to set DRAM DCLK Driving
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// freq 400M, 533M, 667M, 800M
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static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
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static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
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/*
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* Duty cycle
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* Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB
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* D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF
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* According to DRAM frequency to control Duty Cycle
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*/
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static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0xEC, 0x00, 0x30, 0x30, 0x30, 0x30}, // 1Rank
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{0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00},
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{0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30},
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};
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static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0xED, 0x00, 0x88, 0x88, 0x84, 0x88}, // 1Rank
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{0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00},
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{0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00},
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};
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/*
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* DRAM Clock Phase Control for FeedBack Mode
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* Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94
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* Processing:
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* 1. Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode.
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* 2. Program clock phase value with ChA/B DCLK enable,
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* VIA_NB3DRAM_REG91[7:3]=00b
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* 3. Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO
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* ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b.
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*/
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static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank
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{0x92, 0xF8, 0x04, 0x03, 0x03, 0x02},
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{0x93, 0xF8, 0x06, 0x05, 0x04, 0x03},
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};
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static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0x0F, 0x20, 0x10, 0x00, 0x70}, // 1Rank
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{0x92, 0x0F, 0x40, 0x30, 0x30, 0x20},
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{0x93, 0x0F, 0x60, 0x50, 0x40, 0x30},
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};
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/* vt6413c */
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#if 0
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static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank
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{0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 },
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{0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 },
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};
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#endif
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/* vt6413d */
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static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank
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{0x92, 0xF8, 0x04, 0x03, 0x03, 0x02},
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{0x93, 0xF8, 0x06, 0x05, 0x04, 0x03},
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};
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/*
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* DRAM Write Data phase control
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* Modify NB Reg: Rx74/Rx75/Rx76
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*/
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/* vt6413c */
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#if 0
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static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank
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{0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 },
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{0x76, 0x00, 0x10, 0x80, 0x00, 0x07 },
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};
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#endif
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/* vt6413D */
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static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM][WrtData_FREQ_NUM] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0xF8, 0x01, 0x00, 0x00, 0x07}, // 1Rank
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{0x75, 0xF8, 0x01, 0x00, 0x00, 0x07},
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{0x76, 0x10, 0x80, 0x87, 0x07, 0x06},
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{0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03},
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};
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#if 0
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static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank
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{0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 },
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{0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 },
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};
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#endif
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/*
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* DQ/DQS Output Delay Control
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* Modify NB D0F3: RxF0/RxF1/RxF2/RxF3
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*/
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static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = {
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//RxF0 RxF1 RxF2 RxF3
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{0x00, 0x00, 0x00, 0x00}, /* DDR400 */
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{0x00, 0x00, 0x00, 0x00}, /* DDR533 */
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{0x00, 0x00, 0x00, 0x00}, /* DDR667 */
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{0x00, 0x00, 0x00, 0x00}, /* DDR800 */
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};
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static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = {
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//RxF4 RxF5 RxF6 RxF7
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{0x00, 0x00, 0x00, 0x00}, /* DDR400 */
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{0x00, 0x00, 0x00, 0x00}, /* DDR533 */
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{0x00, 0x00, 0x00, 0x00}, /* DDR667 */
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{0x00, 0x00, 0x00, 0x00}, /* DDR800 */
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};
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/*
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* DQ/DQS input Capture Control
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* modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B
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*/
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/* vt6413C */
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#if 0
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static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank
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{0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
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{0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 }
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};
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#endif
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/* vt6413D */
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static const u8DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01}, // 1Rank
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{0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00},
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{0x7B, 0x00, 0x34, 0x34, 0x20, 0x10}
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};
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static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x79, 0x00, 0x89, 0x89, 0x87, 0x83}, // 1Rank
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{0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00},
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{0x8B, 0x00, 0x34, 0x34, 0x20, 0x10}
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};
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static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = {
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//Rx70 Rx71
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{0x00, 0x05}, /* DDR800 */
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{0x00, 0x06}, /* DDR667 */
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{0x00, 0x04}, /* DDR533 */
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{0x00, 0x05}, /* DDR400 */
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};
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static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = {
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//Rx70 Rx71
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{0x00, 0x04}, /* DDR800 */
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{0x00, 0x04}, /* DDR667 */
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{0x00, 0x03}, /* DDR533 */
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{0x00, 0x04}, /* DDR400 */
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};
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