10141c3006
This change may slow down the raminit by maximum 200usec, but reuses the lapic udelay definition. Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17152 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
44 lines
1019 B
Plaintext
44 lines
1019 B
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config NORTHBRIDGE_INTEL_GM45
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bool
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if NORTHBRIDGE_INTEL_GM45
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config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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def_bool y
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select HAVE_DEBUG_RAM_SETUP
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select VGA
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select INTEL_EDID
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select INTEL_GMA_ACPI
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select UDELAY_LAPIC
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config CBFS_SIZE
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hex
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default 0x100000
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/gm45/bootblock.c"
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config VGA_BIOS_ID
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string
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default "8086,2a42"
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endif
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