105d3091f9
Change-Id: I93455f38663cf29d8b5160ac21c94db08eb44fa9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
37 lines
714 B
Plaintext
37 lines
714 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config NORTHBRIDGE_AMD_PI
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bool
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default y if CPU_AMD_PI
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default n
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if NORTHBRIDGE_AMD_PI
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config BOTTOMIO_POSITION
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hex "Bottom of 32-bit IO space"
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default 0xD0000000
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help
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If PCI peripherals with big BARs are connected to the system
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the bottom of the IO must be decreased to allocate such
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devices.
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Declare the beginning of the 128MB-aligned MMIO region. This
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option is useful when PCI peripherals requesting large address
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ranges are present.
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config S3_VGA_ROM_RUN
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bool
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default n
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source "src/northbridge/amd/pi/00730F01/Kconfig"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config HEAP_SIZE
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hex
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default 0xc0000
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endif # NORTHBRIDGE_AMD_PI
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