105f5b737b
Many ChromeOS devices use a GPIO to reset the system, in order to guarantee that the TPM cannot be reset without also resetting the CPU. Often chipset/SoC hardware watchdogs trigger some kind of built-in CPU reset, bypassing this GPIO and thus leaving the TPM locked. These ChromeOS devices need to detect that condition in their bootblock and trigger a second (proper) reboot. This patch adds some code to generalize this previously mainboard-specific functionality and uses it on Veyron boards. It also provides some code to add the proper eventlog entry for a watchdog reset. Since the second reboot has to happen before firmware verification and the eventlog is usually only initialized afterwards, we provide the functionality to place a tombstone in a memlayout-defined location (which could be SRAM or some MMIO register that is preserved across reboots). [pg: Integrates 'mips: Temporarily work around build error caused by <arch/io.h> mismatch] BRANCH=veyron BUG=chrome-os-partner:35705 TEST=Run 'mem w 0xff800000 0x9' on a Jerry, watch how a "Hardware watchdog reset" event appears in the eventlog after the reboot. Change-Id: I0a33820b236c9328b2f9b20905b69cb934326f2a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fffc484bb89f5129d62739dcb44d08d7f5b30b33 Original-Change-Id: I7ee1d02676e9159794d29e033d71c09fdf4620fd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242404 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Id: c919c72ddc9d2e1e18858c0bf49c0ce79f2bc506 Original-Change-Id: I509c842d3393bd810e89ebdf0dc745275c120c1d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242504 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9749 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
79 lines
2.4 KiB
C
79 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <assert.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <delay.h>
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#include <reset.h>
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#include <soc/clock.h>
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#include <soc/i2c.h>
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#include <soc/grf.h>
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#include <soc/pmu.h>
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#include <soc/rk808.h>
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#include <soc/spi.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "board.h"
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void bootblock_mainboard_early_init()
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{
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if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) {
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assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
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writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
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}
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}
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void bootblock_mainboard_init(void)
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{
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/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
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setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
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setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
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assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
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i2c_init(CONFIG_PMIC_BUS, 400*KHz);
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/* Slowly raise to max CPU voltage to prevent overshoot */
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rk808_configure_buck(1, 1200);
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udelay(175);/* Must wait for voltage to stabilize,2mV/us */
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rk808_configure_buck(1, 1400);
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udelay(100);/* Must wait for voltage to stabilize,2mV/us */
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rkclk_configure_cpu();
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if (rkclk_was_watchdog_reset())
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reboot_from_watchdog();
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/* i2c1 for tpm */
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writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
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i2c_init(1, 400*KHz);
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/* spi2 for firmware ROM */
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writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
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writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
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rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
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/* spi0 for chrome ec */
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writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
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setup_chromeos_gpios();
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}
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